Altera Triple Speed Ethernet MegaCore Function - Manual (Page 156)

Avalon-ST Transmit Interface
Figure 7-14: Transmit Operation—MAC With Internal FIFO Buffers
ff_tx_clk
ff_tx_data[31:0]
ff_tx_sop
ff_tx_eop
ff_tx_rdy
ff_tx_wren
ff_tx_crc_fwd
ff_tx_err
ff_tx_mod[1:0]
ff_tx_septy
tx_ff_uflow
00000001 00000002 00000003 00000004 00000005 00000006
Figure 7-15: Transmit Operation—MAC Without Internal FIFO Buffers
mac_tx_clk_0
data_tx_data_0[7:0]
data_tx_sop_0
data_tx_eop_0
data_tx_ready_0
data_tx_err_0
data_tx_valid_0
00 00 01 01 01 02 03 04 05 06 07 08 09
GMII Transmit
On transmit, all data transfers are synchronous to the rising edge of
tx_clk
. The GMII data enable signal
gm_tx_en
is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame
is present on gm_tx_d[7:0] bus. Between frames, gm_tx_en remains deasserted.
If a frame is received on the Avalon-ST interface with an error (asserted with
ff_tx_eop
), the frame is
subsequently transmitted with the GMII
gm_tx_err
error signal at any time during the frame transfer.
GMII Receive
On receive, all signals are sampled on the rising edge of rx_clk . The GMII data enable signal gm_rx_dv is
asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame
is present on the
gm_rx_d[7:0] bus. Between frames, gm_rx_dv remains deasserted.
If the PHY detects an error on the frame received from the line, the PHY asserts the GMII error signal,
gm_rx_err
, for at least one clock cycle at any time during the frame transfer.
A frame received on the GMII interface with a PHY error indication is subsequently transferred on the
Avalon-ST interface with the error signal
rx_err[0] asserted.
Altera Corporation Interface Signals
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7-41 Avalon-ST Transmit Interface
UG-01008
2014.06.30