Altera Triple Speed Ethernet MegaCore Function - Manual (Page 152)

Description I/O Name
Asserted by the PHY to indicate that the current frame contains errors. O
mii_rx_err
Collision detection. Asserted by the PCS function to indicate that a
collision was detected during frame transmission. Out
mii_col
Carrier sense detection. Asserted by the PCS function to indicate that
a transmit or receive activity is detected on the Ethernet line. Out
mii_crs
SGMII Status Signals
The SGMII status signals provide status information to the PCS block. When the PCS is instantiated
standalone, these signals are inputs to the MAC and serve as interface control signals for that block.
Table 7-41: SGMII Status Signals
Description I/O Name
Gigabit mode enabled. In 1000BASE-X, this signal is always set to 1.
In SGMII, this signal is set to 1 if one of the following conditions is
met:
the USE_SGMII_AN bit is set to 1 and a gigabit link is established with
the link partner, as decoded from the
partner_ability
register
the USE_SGMII_AN bit is set to 0 and the SGMII_SPEED bit is set to 10
O
set_1000
100 -Mbps mode enabled. In 1000BASE-X, this signal is always set to
0. In SGMII, this signal is set to 1 if one of the following conditions is
met:
the
USE_SGMII_AN
bit is set to 1 and a 100Mbps link is established
with the link partner, as decoded from the
partner_ability
register
the
USE_SGMII_AN
bit is set to 0 and the
SGMII_SPEED
bit is set to 01
O set_100
10 -Mbps mode enabled. In 1000BASE-X, this signal is always set to
0. In SGMII, this signal is set to 1 if one of the following conditions is
met:
the
USE_SGMII_AN
bit is set to 1 and a 10Mbps link is established with
the link partner, as decoded from the partner_ability register
the
USE_SGMII_AN
bit is set to 0 and the
SGMII_SPEED
bit is set to 00
O
set_10
Half-duplex mode enabled. In 1000BASE-X, this signal is always set
to 0. In SGMII, this signal is set to 1 if one of the following conditions
is met:
the USE_SGMII_AN bit is set to 1 and a half-duplex link is established
with the link partner, as decoded from the
partner_ability
register
the USE_SGMII_AN bit is set to 0 and the SGMII_DUPLEX bit is set to 1
O
hd_ena
Altera Corporation Interface Signals
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7-37 SGMII Status Signals
UG-01008
2014.06.30