Mac error correction code, Mac reset, Mac error correction code -19 mac reset -19 – Altera Triple Speed Ethernet MegaCore Function User Manual

Page 55

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MAC Error Correction Code

The error correction code feature is implemented to memory instances in the MegaCore function. This
feature is capable of detecting single and double bit errors, and can fix single bit errors in the corrupted data.

Table 4-8: Core Variation and ECC Protection Support

ECC Protection Support

Core Variation

Protects the following options:

transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

Statistic counters (if enabled)

Multicast hashtable (if enabled)

10/100/1000 Mb Ethernet MAC

Protects the following options:

transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

Statistic counters (if enabled)

Multicast hashtable (if enabled)

SGMII bridge (if enabled)

10/100/1000 Mb Ethernet MAC with
1000BASE-X/SGMII PCS

Protects the SGMII bridge (if enabled)

1000BASE-X/SGMII PCS only

Protects the transmit and receive FIFO buffer

1000 Mb Small MAC

Protects the following options:

transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

10/100 Mb Small MAC

When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and
1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the MegaCore
function.

• Single channel core configuration—

eccstatus[1:0]

output ports.

• Multi-channel core configuration—

eccstatus_<n>[1:0]

output ports, where

eccstatus_0[1:0]

is for

channel 0, eccstatus_1[1:0] for channel 1, and so on.

MAC Reset

A hardware reset resets all logic. A software reset only disables the transmit and receive paths, clears all
statistics registers, and flushes the receive FIFO buffer. The values of configuration registers, such as the
MAC address and thresholds of the FIFO buffers, are preserved during a software reset.

When you trigger a software reset, the MAC function sets the

TX_ENA

and

RX_ENA

bits in the

command_config

register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only
disabled when the current frame transmission and reception complete.

Altera Corporation

Functional Description

Send Feedback

4-19

MAC Error Correction Code

UG-01008
2014.06.30

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