Phy management (mdio), Phy management (mdio) -20 – Altera Triple Speed Ethernet MegaCore Function User Manual

Page 56

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• To trigger a hardware reset, assert the

reset

signal.

• To trigger a software reset, set the

SW_RESET

bit in the

command_config

register to 1. The

SW_RESET

bit

is cleared automatically when the software reset ends.

Altera recommends that you perform a software reset and wait for the software reset sequence to complete
before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating
speed or mode without changing other configurations, preserve the

command_config

register before

performing the software reset and restore the register after the changing the MAC operating speed or mode.

Figure 4-8: Software Reset Sequence

Receive Frames

Transmit Frames

Flush FIFO

Clear Statistics

Counters

Yes

Yes

Yes

No

No

No

Yes

No

Yes

No

RX _ENA =0

TX _ENA =0

START

(SW_RESET = 1)

END

(SW_RESET = 0)

Frame

Reception

Completed?

Frame

Transmission

Completed?

MAC with

internal FIFO?

Receive

FIFO empty?

Statistics
Counters

Enabled?

If the

SW_RESET

bit is 1 when the line clocks are not available (for example, cable is disconnected),

the statistics registers may not be cleared. The

read_timeout

register is then set to 1 to indicate that

the statistics registers were not cleared.

Note:

PHY Management (MDIO)

This module implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the
PHY device management registers, and supports up to 32 PHY devices.

To access each PHY device, write the PHY address to the MDIO register (

mdio_addr0

/

1

) followed by the

transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to
be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require
writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the
MDIO registers via the Avalon-MM interface.

For more information about the registers of a PHY device, refer to the specification provided with the device.

Functional Description

Altera Corporation

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UG-01008

PHY Management (MDIO)

4-20

2014.06.30

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