Power-down in pcs variations with embedded pma, 1000base-x/sgmii pcs reset, 1000base-x/sgmii pcs reset -34 – Altera Triple Speed Ethernet MegaCore Function User Manual

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When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmit
and the TBI receive interfaces are ignored. The management interface remains active and responds to
management transactions from the MAC layer device.

Figure 4-22: Power-Down

MDIO

Slave

powerdown

Control

Powerdown Control

(Technology Specific)

1000BASE-X PCS

Power-Down in PCS Variations with Embedded PMA

In PCS variations with embedded PMA targeting devices with GX transceivers, the power-down signal is
internally connected to the power-down of the GX transceiver. In these devices, the power-down functionality
is shared across quad-port transceiver blocks. Ethernet designs must share a common

gbx_pwrdn_in

signal

to use the same quad-port transceiver block.

For designs targeting devices other than Stratix V, you can export the power-down signals to implement
your own power-down logic to efficiently use the transceivers within a particular transceiver quad. Turn on
the Export transceiver powerdown signal parameter to export the signals.

Figure 4-23: Power-Down with Export Transceiver Power-Down Signal

PMA

POWERDOWN

CONTROL

pcs_pwrdn_out

gxb_pwrdn_in

1000BASE-X PCS

1000BASE-X/SGMII PCS Reset

A hardware reset resets all logic synchronized to the respective clock domains whereas a software reset only
resets the PCS state machines, comma detection function, and 8B10B encoder and decoder. To trigger a
hardware reset on the PCS, assert the respective reset signals:

reset_reg_clk

,

reset_tx_clk

, and

reset_rx_clk

. To trigger a software reset, set the

RESET

bit in the

control

register to 1.

In PCS variations with embedded PMA, assert the respective reset signals or the power-down signal to trigger
a hardware reset. You must assert the

reset

signal subsequent to asserting the

reset_rx_clk

,

reset_tx_clk

,

or

gbx_pwrdn_in

signal. The reset sequence is also initiated when the active-low

rx_freqlocked

signal goes

low.

Functional Description

Altera Corporation

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UG-01008

Power-Down in PCS Variations with Embedded PMA

4-34

2014.06.30

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