Altera Triple Speed Ethernet MegaCore Function - Manual (Page 195)

Description
Register Write or I/O Pin Assertion (1)
XON_GEN XOFF_GEN
If the
XON_GEN
bit is set to 1, the XON pause frames are
continuously generated and sent to the MII/GMII TX interface
until the
XON_GEN
bit is cleared.
1 0
This event is not recommended as it will produce non-
deterministic result. 1 1
Note to Table A-1 :
1. Set the XON and XOFF registers to 0 when you use the I/O pin to generate the pause frame and vice
versa.
Ethernet Frame Format Altera Corporation
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Pause Frame Generation A-4
2014.06.30