Altera Triple Speed Ethernet MegaCore Function - Manual (Page 206)

HW
Reset
Description R/W Name Dword
Offset
0x0 The drift of ToD adjusted periodically by adding
a correction value as configured in this register
space.
• Bits 0 to 15: Adjustment value in fractional
nanosecond ( DRIFT_ADJUST_FNS ). This value
is added into the current ToD during the
adjustment. The default value is 0.
• Bits 16 to 19: Adjustment value in nanosecond
(
DRIFT_ADJUST_NS
). This value is added into
the current ToD during the adjustment. The
default value is 0.
• Bits 20 to 32: Not used.
RW
DriftAdjust
0x1C
0x0 The count of clock cycles for each ToD’s drift
adjustment to take effect.
• Bits 0 to 15: The number of clock cycles
( ADJUST_RATE ). The ToD adjustment happens
once after every period in number of clock
cycles as indicated by this register space.
• Bits 16 to 32: Not used.
RW DriftAdjustRate 0x20
Adjusting ToD Clock Drift
You can use the DriftAdjust and DriftAdjustRate registers to correct any drift in the ToD clock.
In the case of a ToD for 10G with period of 6.4ns, the nanosecond field is converted directly to PERIOD_NS
while the fractional nanosecond need to be multiplied with 216 or 65536 in order to convert to
PERIOD_FNS
.
This results in 0x6 PERIOD_NS and 0x6666.4 PERIOD_FNS .
PERIOD_NS only accepts 0x6666 and ignores 0x0000.4, which in turn would cause some inaccuracy in the
configured period. This inaccuracy causes the ToD to drift from the actual time as much as 953.67 ns after
a period of 1 second. You would notice that after every 5 cycles, 0x0000.4 accumulates to 0x0002. If the TOD
is able to add 0x0002 of fractional nanosecond into the ToD once after every period of 5 cycles, then it will
correct the drift.
Therefore, for the 10G case,
DRIFT_ADJUST_NS
is now configured to 0x0,
DRIFT_ADJUST_FNS
is configured
to 0x0002 and
ADJUST_RATE
is configured to 0x5.
Time-of-Day (ToD) Clock Altera Corporation
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UG-01008
Adjusting ToD Clock Drift C-6
2014.06.30