Freescale Semiconductor MCF5480 - Manual (Page 1016)

MCF548x Reference Manual, Rev. 3
Index-2 Freescale Semiconductor
configuration/status (CSR) 8-11
data breakpoint/mask (DBR, DBMR) 8-22
extended trigger definition (XTDR) 8-25
PC breakpoint ASID (PBASID) 8-24
PC breakpoint ASID control (PBAC) 8-14
program counter breakpoint/mask (PBRn,
PBMR) 8-20
trigger definition (TDR) 8-17
signals 8-2
taken branch 8-6
virtual environment 5-7
DMA
initiators 24-23
LURC 24-31
master DMA engine 24-27
memory map 24-3
prioritization 24-24
registers
current pointer (CP) 24-7
end pointer (EP) 24-8
external request address mask (EREQMASK) 24-21
external request base address (EREQBAR) 24-20
initiator mux control (IMCR) 24-13
initiator priority (IPRIORn) 24-12
interrupt mask (DIMR) 24-10
interrupt pending (DIPR) 24-10
PTD control (PTD) 24-9
task base address (TaskBAR) 24-6
task control (TCRn) 24-11
task size (TSKSZn) 24-14
variable pointer (VP) 24-8
signals
DACKn 24-3
DREQn 24-3
task initialization 24-23
task instantiation 24-28
task table 24-3
termination of loop 24-27
variable table 24-4
DSPI
baud rate 27-23, 27-33
block diagram 27-2
changing queues 27-33
clock delay 27-23–27-24, 27-34
DMA requests 27-31
FIFO
disabling 27-21
Rx
buffering 27-22
draining 27-22
filling 27-22
Tx
buffering 27-21
draining 27-21
filling 27-21
interrupts 27-31–27-32
memory map 27-4
registers
clock and transfer attributes 0–7 (DCTARn) 27-7
DMA/interrupt request select (DIRSR) 27-13
module configuration (DMCR) 27-5
Rx FIFO (DRFR) 27-16
Rx FIFO debug 0–3 (DRFDRn) 27-17
status (DSR) 27-11
transfer count (DTCR) 27-7
Tx FIFO (DTFR) 27-15
Tx FIFO debug 0–3 (DTFDRn) 27-17
signals
peripheral chip select 5/peripheral chip select strobe
(DSPICS5/PCSS) 27-3
peripheral chip select/slave select
(DSPICS0/SS) 27-3
peripheral chip selects 2–3 (DSPICSn) 27-3
serial clock (DSPISCK) 27-4
serial input (DSPISIN) 27-4
serial output (DSPISOUT) 27-4
start and stop 27-19
transfer formats 27-25–27-30
E
EMAC
data representation 3-17, 4-12
hardware support 3-4
instructions
execution timing 4-11
summary 4-11
MAC, comparison 4-1
memory map 4-5
opcodes 4-13
operation
general 4-2
rounding 4-8
saving and restoring 4-9
registers
mask (MASK) 4-10
status (MACSR) 4-5
EPORT
memory map 14-2
registers
data direction (EPDDR) 14-3
flag (EPFR) 14-5
pin assignment (EPPAR) 14-3
pin data (EPPDR) 14-5
port data (EPDR) 14-4