Freescale Semiconductor Microcontrollers - Manual (Page 318)

HC08 Full Chip Simulation
Configuration Procedure
318 Microcontrollers Debugger Manual
cli ; Allow interrupts to happen
main_loop:
bra main_loop
**************************************************************
* USB_ENDP_ISR - USB Endpoint Interrupt Service Routine. *
* Interrupts here if packets are received or *
* transmitted on any endpoint. *
**************************************************************
USB_ENDP_ISR:
brclr 0,UEP0CSR,USB_ENDP_ISR2 ; Is it an OUT packet received?
brclr 1,UEP0CSR,USB_ENDP_ISR2
jsr OUT_PROC ; handle OUT packet for EP0
rti ; exit interrupt
USB_ENDP_ISR2:
brclr 2,UEP0CSR,USB_ENDP_ISR3 ; Is packet sent from IN packet
; for endpoint 0?
jsr IN_PROC ; handle IN packet for endpoint 0
rti ; exit interrupt
USB_ENDP_ISR3:
brclr 0,UEP1CSR,USB_ENDP_ISR4 ; Is packet sent from IN packet
; for endpoint 1?
lda ptb ; get Port B value
sta EP1BuffStart ; place in endpoint 1 data buffer
mov #01,UEP1DSR ; set data size for endpoint 1
; to 1
bclr 0,UEP1CSR ; clear the TFRC flag
bset 1,UEP1CSR ; set the DVALID flag
USB_ENDP_ISR4:
brclr 0,UEP2CSR,USB_ENDP_EXIT ; is it a packet for endpoint 2?
brclr 1,UEP2CSR,USB_ENDP_EXIT ; is it an OUT packet?
ldhx #0
USB_ISR4_LOOP:
lda EP2BuffStart,x ; get data received in endpoint buffer
sta EP2Data,x ; and transfer to local data buffer
aix #1
cpx UEP2DSR
bne USB_ISR4_LOOP
lda UEP2CSR ; clear the TFRC/DVALID flag
and #$fc
sta UEP2CSR
rti ; exit interrupt
USB_ENDP_EXIT: