Freescale Semiconductor Microcontrollers - Manual (Page 538)

HCS08 On-Chip DBG Module
Limitations
538 Microcontrollers Debugger Manual
Limitations
The following limitations apply in demo/unregistered debugger mode:
• In demo/unregistered debugger mode, code program reconstruction has a limited
number of frames displayed in the Trace window.
• Real time code Profiling and code Coverage are disabled.
• No preset/predefined Instruction Triggers , Memory Access Triggers or Capture
Triggers are provided. Only Expert Triggers can be set.
HCS08 DBG V3 New Features
The following new features are available on version 3 of the HCS08 DBG Module.
MMU and Extended Address Space
By design, the DBG V3 module is compliant with newer devices with the on-chip
Memory Management Unit module, like the MC9S08QE128 devices. The extended
address space memory accesses are supported, and also program flow recording and
rebuild of applications running over PPAGE paging windows (banked memory model).
LOOP1 mode
The on-chip DBG V3 module (available for example on MC9S08QE128 devices)
provides some new features, like an additional comparator that is typically used as a third
hardware breakpoint, that is not involved in the trigger logic except in a new recording
mode call LOOP1. In LOOP1 mode, the DBG module verifies if the last captured change
of flow is already recorded in the DBG fifo database, and if it is the case, the fifo database
is not changed and the capture discarded. This avoids recording short loop changes of flow
that can quickly fill completely the database without providing relevant debug
information. For example, this improves efficiency when executing a DBNZ instruction
by recording instruction branching only once.
Select the LOOP1 module in the Trigger Module Settings dialog by selecting FIFO
LOOP1 mode in a list menu. The genuine mode is called FIFO Normal mode.