Freescale Semiconductor Microcontrollers - Manual (Page 373)

HC08 P&E Multilink/Cyclone Pro Connection
Connection Procedure
373 Microcontrollers Debugger Manual
– No Power to the ICS.
If this status bit returns an ‘N’, you must correct this before analyzing the rest of the
status bits.
• 2 – Device echoed all security bytes:
To pass security, the software must send eight security bytes to the processor. The
processor echoes each of these eight bytes twice. If all eight bytes do not get the
proper two-byte echo, this flag returns an ‘N’. Reasons for this include:
– The part did not start the monitor mode security check on reset. Signals to force
monitor mode may be incorrect.
– The baud rate specified was incorrect.
– The processor was not reset properly. Check the Target Hardware Type and, if
you are connecting to a class II board, check the MON08 cable communication
connections type in the Advanced Settings dialog box.
• 3 – Device signaled monitor mode with a break:
Once the processor has properly received the eight bytes from the PC software to
complete its security check, it transmits a break character to the PC signaling entry
into monitor mode. This break is sent regardless of whether the security check was
successfully passed. If a break was not received from the processor, this flag returns
an ‘N’. Reasons for this include:
– The baud rate specified was incorrect.
– The processor was not reset properly. Check the Target Hardware Type. If you
are connecting to a class II board, check the MON08 cable communication
connections type in the Advanced Settings dialog box.
• 4 – Device entered monitor mode:
Once the software has received, or failed to receive, a break from the processor, it
attempts to communicate with the monitor running on the M68HC08 processor. It
tries to read the monitor version number by issuing a monitor mode read. If the
processor fails to respond properly to this command, this flag returns an ‘N’.
• 5 – Reset was Power-On Reset:
If the device properly entered monitor mode (4), the software reads the reset status
register (RSR). This read does not affect the security sequence, and occurs purely for
diagnostic reasons. The RSR indicates the conditions under which the processor
underwent the last reset. For the software to pass the security check properly, it
MUST first cause the processor to undergo a Power-On Reset. The software reads
the RSR to determine if the last reset was indeed caused by power-on. The result of
the RSR read is indicated in parentheses after the flag value. If the highest bit is not
set then the reset was not a power on reset, and the flag indicates an ‘N’. Reasons for
this include: