AltiGen MAXCS 7.0 Update 1 ACM Administration - Manual (Page 133)

Configuring the Triton T1/E1 Board
MaxCS 7.5 Administration Manual 117
Setting the Configurable Options
These are the options you can set:
Option Notes
Frame Type
• For T1, you can set the Frame Type to either SF or ESF. SF
(Superframe Format) consists of 12 consecutive frames. ESF
(Extended Superframe Format) consists of 24 consecutive frames.
• For E1, you can set the Frame Type to either No CRC or CRC4. CRC4
is embedded into 16 consecutive frames.
Line Code
• For T1, you can set the Line Code to either AMI or B8ZS. AMI (Alter-
nate Mark Inversion) is the line coding format in T1 transmission sys-
tems whereby successive ones (marks) are alternately inverted and
sent with opposite polarity of the preceding mark. B8ZS (Binary 8 Zero
Substitution) sends two violations of the bipolar line encoding tech-
nique, rather than inserting a one for every seven consecutive zeros.
• For E1, you can set the Line Code to either AMI or HDB3. HDB3 (High
Density Bipolar Order) is based on AMI, but extends this by inserting
violation codes whenever there is a run of four or more zeros.
Zero Code Suppression
You can set the Zero Code Suppression to None (default setting), Jam
Bit 8
, GTE or Bell.
Zero Code Suppression inserts a “one” bit to prevent the transmission of
eight or more consecutive “zero” bits; Jam Bit 8 forces every bit 8 to a one;
GTE
Zero Code Suppression replaces bit 8 of an all zero channel byte to
a one, except in signaling frames where bit 7 is forced to a one. Bell Zero
Code Suppression replaces bit 7 of an all zero channel byte with a one.
CD Bits Handling CD Bits Handling is not editable.
System Clock Master
You can set the System Clock Master if you have a back-to-back config-
uration and you want this span to be the master clock to the system. (Only
one clock master should be selected in a back-to-back system.) See the
following section on T1/E1 clocking.
T1/E1 Clocking
Depending on the configuration of the T1/E1 boards and span for your MAXCS system(s), the System Clock
Master
setup should be set according to the follow conditions:
• If all of the T1/E1 boards are connected to a carrier’s switch, the System Clock Master check box must
not
be checked for any of the T1/E1 boards.
• If two MAXCS systems are connected back-to-back with a T1/E1 span, the System Clock Master check
box must be checked for only one of the T1/E1 boards.
• If two T1/E1 boards in the same MAXCS system are connected back-to-back with a T1/E1 span, the
System Clock Master
check box must be checked for the T1/E1 board that has not been designated by
the CT-Bus setting as the system’s master clock to drive the CT-Bus.
Important: For all back-to-back cases, the CT-Bus Clock Configuration should be set to “Manual,” and the
board that is connected to the board configured as the back-to-back clock master must be
designated at the CT-Bus master.
Setting up Channels on the Triton T1/E1 Board
This section discusses setting up T1 CAS, T1 PRI, E1 CAS, or E1 PRI channels on the Triton T1/E1 board.
Click the Protocol button in the T1 or E1 configuration dialog box (see (see Figure
64)) to open the Protocol
Configuration window, shown below. The Triton T1/E1 Board can be configured to either CAS or PRI through
the configuration options in the window.