NXP Semiconductors LPC24XX UM10237 - Manual (Page 113)

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User manual Rev. 04 — 20 August 2009 113 of 792
NXP Semiconductors
UM10237
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
3.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)
This is a read/write accessible register. This register controls which of the 32 combined
hardware and software interrupt requests are enabled to contribute to FIQ or IRQ.
3.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)
This is a write only register. This register allows software to clear one or more bits in the
Interrupt Enable register (see
Section 7–3.4 “Interrupt Enable Register (VICIntEnable -
0xFFFF F010)” on page 113 ), without having to first read it.
3.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)
This is a read/write accessible register. This register classifies each of the 32 interrupt
requests as contributing to FIQ or IRQ.
Table 105. Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description
Bit Symbol Value Description Reset
value
31:0 See Table
7–117
“Interrupt
sources bit
allocation
table”
.
0 Neither the hardware nor software interrupt request with this
bit number are asserted. -
1 The hardware or software interrupt request with this bit
number is asserted.
Table 106. Interrupt Enable register (VICIntEnable - address 0xFFFF F010) bit description
Bit Symbol Description Reset
value
31:0 See Table
7–117
“Interrupt
sources bit
allocation
table”
.
When this register is read, 1s indicate interrupt requests or software
interrupts that are enabled to contribute to FIQ or IRQ.
When this register is written, ones enable interrupt requests or
software interrupts to contribute to FIQ or IRQ, zeroes have no
effect. See
Section 7–3.5 “Interrupt Enable Clear Register
(VICIntEnClear - 0xFFFF F014)” on page 113 and Table 7–107
below for how to disable interrupts.
0
Table 107. Interrupt Enable Clear register (VICIntEnClear - address 0xFFFF F014) bit
description
Bit Symbol Value Description Reset
value
31:0 See Table
7–117
“Interrupt
sources bit
allocation
table”
.
0 Writing a 0 leaves the corresponding bit in VICIntEnable
unchanged. -
1 Writing a 1 clears the corresponding bit in the Interrupt
Enable register, thus disabling interrupts for this request.