NXP Semiconductors LPC24XX UM10237 - Manual (Page 84)

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User manual Rev. 04 — 26 August 2009 84 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.10 Dynamic Memory Last Data Out to Active Time register
(EMCDynamictAPR - 0xFFE0 803C)
The EMCDynamicTAPR register enables you to program the last-data-out to active
command time, tAPR. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tAPR. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selectsmust be programmed.
Table 5–77 shows the bit assignments for the EMCDynamicTAPR register.
10.11 Dynamic Memory Data-in to Active Command Time register
(EMCDynamictDAL - 0xFFE0 8040)
The EMCDynamicTDAL register enables you to program the data-in to active command
time, tDAL. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tDAL, or tAPW. This register is accessed with
one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–78 shows the bit assignments for the EMCDynamicTDAL register.
Table 76. Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX - address
0xFFE0 8038) bit description
Bit Symbol Value Description Reset
Value
3:0 Self-refresh exit
time (tSREX) 0x0 -
0xE n + 1 clock cycles. The delay is in CCLK cycles. 0xF
0xF 16 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 77. Memory Last Data Out to Active Time register (EMCDynamictAPR - address
0xFFE0 803C) bit description
Bit Symbol Value Description Reset
Value
3:0 Last-data-out to
active command
time (tAPR) 0x0 -
0xE n + 1 clock cycles. The delay is in CCLK cycles. 0xF
0xF 16 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA