NXP Semiconductors LPC24XX UM10237 - Manual (Page 83)

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User manual Rev. 04 — 26 August 2009 83 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.8 Dynamic Memory Active to Precharge Command Period register
(EMCDynamictRAS - 0xFFE0 8034)
The EMCDynamicTRAS register enables you to program the active to precharge
command period, tRAS. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tRAS. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–75 shows the bit assignments for the EMCDynamicTRAS register.
10.9 Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX
- 0xFFE0 8038)
The EMCDynamicTSREX register enables you to program the self-refresh exit time,
tSREX. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tSREX, for devices without this parameter you
use the same value as tXSR. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selectsmust be programmed.
Table 5–76 shows the bit assignments for the EMCDynamicTSREX register.
Table 74. Dynamic Memory Percentage Command Period register (EMCDynamictRP -
address 0xFFE0 8030) bit description
Bit Symbol Value Description Reset
Value
3:0 Precharge
command
period (tRP) 0x0 -
0xE n + 1 clock cycles. The delay is in EMCCLK cycles. 0x0F
0xF 16 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 75. Dynamic Memory Active to Precharge Command Period register
(EMCDynamictRAS - address 0xFFE0 8034) bit description
Bit Symbol Value Description Reset
Value
3:0 Active to
precharge
command
period (tRAS) 0x0 -
0xE n + 1 clock cycles. The delay is in EMCCLK cycles. 0xF
0xF 16 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA