Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
Page 122
UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
122 of 792
NXP Semiconductors
UM10237
Chapter 8: LPC24XX Pin configuration
1
TDO
2
P3[11]/D11
3
P3[10]/D10
4
V
SSIO
5
P1[0]/ENET_TXD0
6
P1[8]/ENET_CRS_DV/
ENET_CRS
7
P1[2]/ENET_TXD2/
MCICLK/PWM0[1]
8
P1[16]/ENET_MDC
9
P4[29]/BLS3/
MAT2[1]/RXD3
10
P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
11
P0[5]/I2SRX_WS/TD2/
CAP2[1]
12
P0[7]/I2STX_CLK/SCK1
/MAT2[1]
13
P1[5]/ENET_TX_ER/
MCIPWR/PWM0[3]
14
P4[13]/A13
15
-
16
-
Row C
1
P3[13]/D13
2
TMS
3
TDI
4
RTCK
5
V
DD(3V3)
6
P1[4]/ENET_TX_EN
7
P4[30]/CS0
8
P4[24]/OE
9
P1[17]/ENET_MDIO
10
P4[15]/A15
11
V
SSIO
12
P0[8]/I2STX_WS/
MISO1/MAT2[2]
13
P1[7]/ENET_COL/
MCIDAT1/PWM0[5]
14
P2[1]/PWM1[2]/RXD1/
PIPESTAT0
15
-
16
-
Row D
1
P0[26]/AD0[3]/
AOUT/RXD3
2
TCK
3
P3[4]/D4
4
TRST
5
P0[2]/TXD0
6
P3[0]/D0
7
P1[9]/ENET_RXD0
8
P1[14]/ENET_RX_ER
9
P4[25]/WE
10
P4[28]/BLS2/
MAT2[0]/TXD3
11
P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
12
P2[0]/PWM1[1]/TXD1/
TRACECLK
13
V
SSIO
14
P1[13]/ENET_RX_DV
15
-
16
-
Row E
1
P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
2
V
DD(3V3)
3
P3[5]/D5
4
P0[25]/AD0[2]/
I2SRX_SDA/TXD3
5
DBGEN
6
P3[1]/D1
7
P4[31]/CS1
8
P4[14]/A14
9
V
DD(DCDC)(3V3)
10
V
DD(3V3)
11
P2[2]/PWM1[3]/
CTS1/PIPESTAT1
12
V
DD(3V3)
13
P2[3]/PWM1[4]/
DCD1/PIPESTAT2
14
P2[4]/PWM1[5]/
DSR1/TRACESYNC
15
-
16
-
Row F
1
P3[14]/D14
2
V
DDA
3
V
SSA
4
P3[6]/D6
5
P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0]
6
7
8
9
10
P4[12]/A12
11
P4[11]/A11
12
P2[5]/PWM1[6]/
DTR1/TRACEPKT0
13
P2[6]/PCAP1[0]/
RI1/TRACEPKT1
14
P4[27]/BLS1
15
-
16
-
Row G
1
V
DD(DCDC)(3V3)
2
VREF
3
P3[7]/D7
4
P3[15]/D15
5
P3[3]/D3
6
7
8
9
10
NC
11
P2[7]/RD2/
RTS1/TRACEPKT2
12
P4[10]/A10
13
V
SSIO
14
P2[8]/TD2/
TXD2/TRACEPKT3
15
-
16
-
Row H
Table 119. LPC2458 pin allocation table
…continued
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol