NXP Semiconductors LPC24XX UM10237 - Manual (Page 767)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 767 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
Table 345.USB System Error Interrupt Clear register
(USBSysErrIntClr - address 0xFFE0 C2BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .360
Table 346.USB System Error Interrupt Set register
(USBSysErrIntSet - address 0xFFE0 C2C0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .360
Table 347.SIE command code table . . . . . . . . . . . . . . . .364
Table 348.Device Set Address Register bit description. .364
Table 349.Configure Device Register bit description. . . .365
Table 350.Set Mode Register bit description. . . . . . . . . .365
Table 351.Set Device Status Register bit description . . .366
Table 352.Get Error Code Register bit description . . . . .368
Table 353.Read Error Status Register bit description . . .368
Table 354.Select Endpoint Register bit description . . . . .369
Table 355.Set Endpoint Status Register bit description. .370
Table 356.Clear Buffer Register bit description . . . . . . . .371
Table 357.DMA descriptor . . . . . . . . . . . . . . . . . . . . . . . .376
Table 358.USB (OHCI) related acronyms and abbreviations
used in this chapter . . . . . . . . . . . . . . . . . . . .389
Table 359.USB OTG port pins. . . . . . . . . . . . . . . . . . . . .390
Table 360.USB Host register address definitions . . . . . .392
Table 361.USB OTG port 1 pins . . . . . . . . . . . . . . . . . . .396
Table 362.USB OTG and I2C register address
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
Table 363.USB Interrupt Status register - (USBIntSt -
address 0xE01F C1) bit description . . . . . . . .401
Table 364.OTG Interrupt Status register (OTGIntSt - address
0xE01F C100) bit description . . . . . . . . . . . . .402
Table 365.OTG Status Control register (OTGStCtrl - address
0xFFE0 C110) bit description . . . . . . . . . . . . .403
Table 366.Port function truth table. . . . . . . . . . . . . . . . . .404
Table 367.OTG Timer register (OTGTmr - address
0xFFE0 C114) bit description . . . . . . . . . . . . .404
Table 368.OTG_clock_control register (OTG_clock_control -
address 0xFFE0 CFF4) bit description . . . . . .404
Table 369.OTG_clock_status register (OTGClkSt - address
0xFFE0 CFF8) bit description. . . . . . . . . . . . .405
Table 370.I2C Receive register (I2C_RX - address
0xFFE0 C300) bit description . . . . . . . . . . . . .406
Table 371.I2C Transmit register (I2C_TX - address
0xFFE0 C300) bit description . . . . . . . . . . . . .406
Table 372.I2C status register (I2C_STS - address
0xFFE0 C304) bit description . . . . . . . . . . . . .407
Table 373.I2C Control register (I2C_CTL - address
0xFFE0 C308) bit description . . . . . . . . . . . . .408
Table 374.I2C_CLKHI register (I2C_CLKHI - address
0xFFE0 C30C) bit description. . . . . . . . . . . . .409
Table 375.I2C_CLKLO register (I2C_CLKLO - address
0xFFE0 C310) bit description . . . . . . . . . . . . .410
Table 376.UART0 Pin description . . . . . . . . . . . . . . . . . .423
Table 377.UART Register Map . . . . . . . . . . . . . . . . . . . .425
Table 378.UARTn Receiver Buffer Register (U0RBR -
address 0xE000 C000, U2RBR - 0xE007 8000,
U3RBR - 0E007 C000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . .427
Table 379.UART0 Transmit Holding Register (U0THR -
address 0xE000 C000, U2THR - 0xE007 8000,
U3THR - 0xE007 C000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 427
Table 380.UARTn Divisor Latch LSB Register (U0DLL -
address 0xE000 C000, U2DLL - 0xE007 8000,
U3DLL - 0xE007 C000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Table 381.UARTn Divisor Latch MSB Register (U0DLM -
address 0xE000 C004, U2DLM - 0xE007 8004,
U3DLM - 0xE007 C004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Table 382.UARTn Interrupt Enable Register (U0IER -
address 0xE000 C004, U2IER - 0xE007 8004,
U3IER - 0xE007 C004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Table 383.UARTn Interrupt Identification Register (U0IIR -
address 0xE000 C008, U2IIR - 0x7008 8008,
U3IIR - 0x7008 C008, Read Only)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 429
Table 384.UARTn Interrupt Handling . . . . . . . . . . . . . . . 430
Table 385.UARTn FIFO Control Register (U0FCR - address
0xE000 C008, U2FCR - 0xE007 8008, U3FCR -
0xE007 C008, Write Only) bit description . . . 431
Table 386.UARTn Line Control Register (U0LCR - address
0xE000 C00C, U2LCR - 0xE007 800C, U3LCR -
0xE007 C00C) bit description . . . . . . . . . . . . 432
Table 387.UARTn Line Status Register (U0LSR - address
0xE000 C014, U2LSR - 0xE007 8014, U3LSR -
0xE007 C014, Read Only) bit description . . . 432
Table 388.UARTn Scratch Pad Register (U0SCR - address
0xE000 C01C, U2SCR - 0xE007 801C, U3SCR -
0xE007 C01C) bit description . . . . . . . . . . . . 434
Table 389.UARTn Auto-baud Control Register (U0ACR -
0xE000 C020, U2ACR - 0xE007 8020, U3ACR -
0xE007 C020) bit description. . . . . . . . . . . . . 434
Table 390.IrDA Control Register for UART3 only (U3ICR -
address 0xE007 C024) bit description . . . . . . 437
Table 391.IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . . 437
Table 392.UARTn Fractional Divider Register (U0FDR -
address 0xE000 C028, U2FDR - 0xE007 8028,
U3FDR - 0xE007 C028) bit description . . . . . 438
Table 393.Fractional Divider setting look-up table . . . . . 440
Table 394.UARTn Transmit Enable Register (U0TER -
address 0xE000 C030, U2TER - 0xE007 8030,
U3TER - 0xE007 C030) bit description . . . . . 441
Table 395:UART1 Pin Description . . . . . . . . . . . . . . . . . 444
Table 396.UART1 register map . . . . . . . . . . . . . . . . . . . 445
Table 397.UART1 Receiver Buffer Register (U1RBR -
address 0xE001 0000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . 447
Table 398.UART1 Transmitter Holding Register (U1THR -
address 0xE001 0000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 447
Table 399.UART1 Divisor Latch LSB Register (U1DLL -
address 0xE001 0000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Table 400.UART1 Divisor Latch MSB Register (U1DLM -
address 0xE001 0004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Table 401.UART1 Interrupt Enable Register (U1IER -