Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

Page 357

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UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

357 of 792

NXP Semiconductors

UM10237

Chapter 13: LPC24XX USB device controller

9.8.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xFFE0 C294)

Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to
generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn
is a read/write register.

9.8.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0xFFE0 C2A0)

When the DMA transfer completes for the current DMA descriptor, either normally
(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in
this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
USBEoTIntSt is a read only register.

Table 336. USB DMA Interrupt Status register (USBDMAIntSt - address 0xFFE0 C290) bit

description

Bit

Symbol

Value Description

Reset
value

0

EOT

End of Transfer Interrupt bit.

0

0

All bits in the USBEoTIntSt register are 0.

1

At least one bit in the USBEoTIntSt is set.

1

NDDR

New DD Request Interrupt bit.

0

0

All bits in the USBNDDRIntSt register are 0.

1

At least one bit in the USBNDDRIntSt is set.

2

ERR

System Error Interrupt bit.

0

0

All bits in the USBSysErrIntSt register are 0.

1

At least one bit in the USBSysErrIntSt is set.

31:3 -

-

Reserved, user software should not write
ones to reserved bits. The value read from a
reserved bit is not defined.

NA

Table 337. USB DMA Interrupt Enable register (USBDMAIntEn - address 0xFFE0 C294) bit

description

Bit

Symbol

Value Description

Reset
value

0

EOT

End of Transfer Interrupt enable bit.

0

0

The End of Transfer Interrupt is disabled.

1

The End of Transfer Interrupt is enabled.

1

NDDR

New DD Request Interrupt enable bit.

0

0

The New DD Request Interrupt is
disabled.

1

The New DD Request Interrupt is
enabled.

2

ERR

System Error Interrupt enable bit.

0

0

The System Error Interrupt is disabled.

1

The System Error Interrupt is enabled.

31:3 -

-

Reserved, user software should not write
ones to reserved bits. The value read
from a reserved bit is not defined.

NA

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