NXP Semiconductors LPC24XX UM10237 - Manual (Page 526)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 526 of 792
1. Basic configuration
The SPI is configured using the following registers:
1. Power: In the PCONP register ( Table 4–63 ), set bit PCSPI.
Remark: On reset, the SPI is enabled (PCSPI = 1).
2. Clock: In PCLK_SEL0 select PCLK_SPI (see Table 4–56 ). In master mode, the clock
must be scaled down (see Section 19–7.4 ).
3. Pins: Select SPI pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to
PINMODE4 (see Section 9–5 ).
4. Interrupts: Interrupts are enabled in the S0SPINT register Section 19–7.7 . Interrupts
are enabled in the VIC using the VICIntEnable register ( Table 7–106 ).
Remark: In the VIC, the SPI shares its interrupts with the SSP0 interface.
2. Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex Communication.
• SPI master or slave.
• Maximum data bit rate of one eighth of the input clock rate.
• 8 to 16 bits per transfer.
3. SPI overview
SPI is a full duplex serial interfaces. It can handle multiple masters and slaves being
connected to a given bus. Only a single master and a single slave can communicate on
the interface during a given data transfer. During a data transfer the master always sends
8 to 16 bits of data to the slave, and the slave always sends a byte of data to the master.
4. SPI data transfers
Figure 19–94 is a timing diagram that illustrates the four different data transfer formats
that are available with the SPI. This timing diagram illustrates a single 8 bit data transfer.
The first thing you should notice in this timing diagram is that it is divided into three
horizontal parts. The first part describes the SCK and SSEL signals. The second part
describes the MOSI and MISO signals when the CPHA variable is 0. The third part
describes the MOSI and MISO signals when the CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with
CPOL set to both 0 and 1. The second point to note is the activation and de-activation of
the SSEL signal. When CPHA = 0, the SSEL signal will always go inactive between data
transfers. This is not guaranteed when CPHA = 1 (the signal can remain active).
UM10237
Chapter 19: LPC24XX SPI
Rev. 04 — 26 August 2009 User manual