NXP Semiconductors LPC24XX UM10237 - Manual (Page 360)

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User manual Rev. 04 — 26 August 2009 360 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
9.8.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0xFFE0 C2C0)
Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntSet is a write only register.
10. Interrupt handling
This section describes how an interrupt event on any of the endpoints is routed to the
Vectored Interrupt Controller (VIC). For a diagram showing interrupt event handling, see
Figure 13–47 .
All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet has been succesfully transmitted or when a NAK
signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see
Section 13–11.3 . For isochronous endpoints, a frame interrupt is generated every 1 ms.
The interrupt handling is different for Slave and DMA mode.
Slave mode
If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the
USBEpIntEn register, the corresponding status bit in the USBEpIntSt is set. For
non-isochronous endpoints, all endpoint interrupt events are divided into two types by the
corresponding USBEpIntPri[n] registers: fast endpoint interrupt events and slow endpoint
interrupt events. All fast endpoint interrupt events are ORed and routed to bit EP_FAST in
the USBDevIntSt register. All slow endpoint interrupt events are ORed and routed to the
EP_SLOW bit in USBDevIntSt.
For isochronous endpoints, the FRAME bit in USBDevIntSt is set every 1 ms.
The USBDevIntSt register holds the status of all endpoint interrupt events as well as the
status of various other interrupts (see
Section 13–9.3.2 ). By default, all interrupts (if
enabled in USBDevIntEn) are routed to the USB_INT_REQ_LP bit in the USBIntSt
Table 345. USB System Error Interrupt Clear register (USBSysErrIntClr - address
0xFFE0 C2BC) bit description
Bit Symbol Value Description Reset
value
31:0 EPxx Clear endpoint xx (2
≤
xx
≤
31) System Error Interrupt request. 0
0 No effect.
1 Clear the EPxx System Error Interrupt request in the
USBSysErrIntSt register.
Table 346. USB System Error Interrupt Set register (USBSysErrIntSet - address 0xFFE0
C2C0) bit description
Bit Symbol Value Description Reset
value
31:0 EPxx Set endpoint xx (2
≤
xx
≤
31) System Error Interrupt request. 0
0 No effect.
1 Set the EPxx System Error Interrupt request in the
USBSysErrIntSt register.