NXP Semiconductors LPC24XX UM10237 - Manual (Page 429)

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User manual Rev. 04 — 26 August 2009 429 of 792
NXP Semiconductors
UM10237
Chapter 16: LPC24XX UART0/2/3
4.5 UARTn Interrupt Identification Register (U0IIR - 0xE000 C008, U2IIR -
0xE007 8008, U3IIR - 0x7008 C008, Read Only)
The UnIIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during
an UnIIR access, the interrupt is recorded for the next UnIIR access.
Bit UnIIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in
Table 16–384 . Given the status of UnIIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The UnIIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UARTn RLS interrupt (UnIIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UARTn Rx input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UARTn Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon an UnLSR read.
Table 383. UARTn Interrupt Identification Register (U0IIR - address 0xE000 C008,
U2IIR - 0x7008 8008, U3IIR - 0x7008 C008, Read Only) bit description
Bit Symbol Value Description Reset
Value
0 IntStatus
0
Interrupt status. Note that U1IIR[0] is active low. The
pending interrupt can be determined by evaluating
UnIIR[3:1]. 1
At least one interrupt is pending.
1 No interrupt is pending.
3:1 IntId
011
Interrupt identification. UnIER[3:1] identifies an interrupt
corresponding to the UARTn Rx FIFO. All other
combinations of UnIER[3:1] not listed above are reserved
(000,100,101,111). 0
1 - Receive Line Status (RLS).
010 2a - Receive Data Available (RDA).
110 2b - Character Time-out Indicator (CTI).
001 3 - THRE Interrupt
5:4 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
7:6 FIFO Enable These bits are equivalent to UnFCR[0]. 0
8 ABEOInt End of auto-baud interrupt. True if auto-baud has finished
successfully and interrupt is enabled. 0
9 ABTOInt Auto-baud time-out interrupt. True if auto-baud has timed
out and interrupt is enabled. 0
31:10 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA