NXP Semiconductors LPC24XX UM10237 - Manual (Page 619)

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User manual Rev. 04 — 26 August 2009 619 of 792
NXP Semiconductors
UM10237
Chapter 23: LPC24XX I 2 S interface
System signaling occurs when a level detection is true and enabled.
Table 542. Conditions for FIFO level comparison
Level Comparison Condition
dmareq_tx_1 tx_depth_dma1 >= tx_level
dmareq_rx_1 rx_depth_dma1 <= rx_level
dmareq_tx_2 tx_depth_dma2 >= tx_level
dmareq_rx_2 rx_depth_dma2 <= rx_level
irq_tx tx_depth_irq >= tx_level
irq_rx rx_depth_irq <= rx_level
Table 543. DMA and interrupt request generation
System Signaling Condition
irq (irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable
dmareq[0] (dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 &
rx_dma1_enable )
dmareq[1] ( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 &
rx_dma2_enable )
Table 544. Status feedback in the I2SSTATE register
Status Feedback Status
irq irq_rx | irq_tx
dmareq1 (dmareq_tx_1 | dmareq_rx_1)
dmareq2 (dmareq_rx_2 | dmareq_tx_2)