NXP Semiconductors LPC24XX UM10237 - Manual (Page 323)

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User manual Rev. 04 — 26 August 2009 323 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
8. LCD timing diagrams
(1) The active data lines will vary with the type of STN panel (4-bit, 8-bit, color, mono) and with single or dual frames.
(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.
(3) The duration of the LCDLP signal is controlled by the HSW field in the LCD_TIMH register.
(4) The Polarity of the LCDLP signal is determined by the IHS bit in the LCD_POL register.
Fig 41. Horizontal timing for STN displays
pixel clock
(internal)
LCD_TIMH (HSW)
LCDLP
(line synch
pulse)
suppressed
during LCDLP
LCD_TIMH (HBP)
16 × LCD_TIMH(PPL) + 1 LCD_TIMH (HFP)
LCDDCLK
(panel clock)
horizontal back porch
(defined in pixel clocks)
horizontal front porch
(defined in pixel clocks)
one horizontal line of LCD data
LCDVD[15:0]
(panel data)
one horizontal line