NXP Semiconductors LPC24XX UM10237 - Manual (Page 568)

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User manual Rev. 04 — 26 August 2009 568 of 792
NXP Semiconductors
UM10237
Chapter 21: LPC24XX SD/MMC card interface
6.9 Data Control Register (MCIDataCtrl - 0xE008 C02C)
The MCIDataCtrl register controls the DPSM. Table 21–501 shows the bit assignment of
the MCIDataCtrl register.
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
Data transfer starts if 1 is written to the enable bit. Depending on the direction bit, the
DPSM moves to the WAIT_S or WAIT_R state. It is not necessary to clear the enable bit
after the data transfer. BlockSize controls the data block length if Mode is 0, as shown in
Table 21–502 .
6.10 Data Counter Register (MCIDataCnt - 0xE008 C030)
The MCIDataCnt register loads the value from the data length register (see Section
21–6.8 “Data Length Register (MCIDataLength - 0xE008 C028)” ) when the DPSM moves
from the IDLE state to the WAIT_R or WAIT_S state. As data is transferred, the counter
decrements the value until it reaches 0. The DPSM then moves to the IDLE state and the
data status end flag is set.
Table 21–503 shows the bit assignment of the MCIDataCnt
register.
Table 501: Data Control register (MCIDataCtrl - address 0xE008 C02C) bit description
Bit Symbol Value Description Reset
Value
0 Enable Data transfer enable. 0
1 Direction Data transfer direction: 0
0 From controller to card.
1 From card to controller.
2 Mode Data transfer mode: 0
0 Block data transfer.
1 Stream data transfer.
3 DMAEnable Enable DMA: 0
0 DMA disabled.
1 DMA enabled.
7:4 BlockSize Data block length 0
31:8 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 502: Data Block Length
Block Size Block Length
0 2 0 = 1 byte.
1 2 1 = 2 bytes.
... -
11 2 11 = 2048 bytes.
12:15 Reserved.