NXP Semiconductors LPC24XX UM10237 - Manual (Page 636)

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User manual Rev. 04 — 26 August 2009 636 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
5. The maximum number of match registers is increased to 7 in order to allow support
for up to 3 double edge PWM channels. This includes the necessary match outputs,
control bits, etc. for each match register:
– Three new Match registers are added, creating Match channels 4 through 6.
– Three additional sets of stop (S), reset (R), and interrupt (I) bits are added to the
MCR register (3 per additional match register).
6. Add PWM outputs to the timer that connect a functional equivalent of an RS Flip-Flop
to two match outputs. A 2-to-1 mux on each PWM output allows selection of either a
single or a double edged PWM. A new register (PCR) is added to hold the control bits
for the muxes (PWMSEL bits).
7. Three interrupt bits are added to the IR register.
A sample of how PWM values relate to waveform outputs is shown in Figure 25–133 .
PWM output logic is shown in Figure 25–132 that allows selection of either single or
double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits. The
match register selections for various PWM outputs is shown in
Table 25–554 . This
implementation of the PWM module supports up to N-1 single edge PWM outputs or
(N-1)/2 double edge PWM outputs, where N is the number of match registers that are
implemented. PWM types can be mixed if desired.For LPC2400 devices N = 7 which
gives up to 6 single edge PWM outputs or up to 3 double edge PWM outputs available at
the same time
The waveforms below show a single PWM cycle and demonstrate PWM outputs under the
following conditions:
The timer is configured for PWM mode (counter resets to one).
Match 0 is configured to reset the timer/counter when a match event occurs.
Control bits PWMSEL2 and PWMSEL4 are set.
The Match register values are as follows:
MR0 = 100 (PWM rate)
MR1 = 41, MR2 = 78 (PWM2 output)
MR3 = 53, MR4 = 27 (PWM4 output)
MR5 = 65 (PWM5 output)
Fig 133. Sample PWM waveforms
PWM2
PWM4
PWM5
100
(counter is reset)
1 27 41 53 65 78