NXP Semiconductors LPC24XX UM10237 User Manual
Page 367
UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
367 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
11.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
The Get Device Status command returns the Device Status Register. Reading the device
status returns 1 byte of data. The bit field definition is same as the Set Device Status
Register as shown in
Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared
before executing the Get Device Status command.
11.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
Different error conditions can arise inside the SIE. The Get Error Code command returns
the last error code that occurred. The 4 least significant bits form the error code.
3
SUS_CH
Suspend (SUS) bit change indicator. The SUS bit can toggle
because:
•
The device goes into the suspended state.
•
The device is disconnected.
•
The device receives resume signalling on its upstream port.
This bit is cleared when read.
0
0
SUS bit not changed.
1
SUS bit changed. At the same time a DEV_STAT interrupt is
generated.
4
RST
Bus Reset bit. On a bus reset, the device will automatically go to
the default state. In the default state:
•
Device is unconfigured.
•
Will respond to address 0.
•
Control endpoint will be in the Stalled state.
•
All endpoints are unrealized except control endpoints EP0
and EP1.
•
Data toggling is reset for all endpoints.
•
All buffers are cleared.
•
There is no change to the endpoint interrupt status.
•
DEV_STAT interrupt is generated.
Note: Bus resets are ignored when the device is not connected
(CON=0).
0
0
This bit is cleared when read.
1
This bit is set when the device receives a bus reset. A DEV_STAT
interrupt is generated.
7:5
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
Table 351. Set Device Status Register bit description
Bit
Symbol
Value
Description
Reset
value