NXP Semiconductors LPC24XX UM10237 - Manual (Page 81)

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User manual Rev. 04 — 26 August 2009 81 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh -
0xFFE0 8024)
The EMCDynamicRefresh register configures dynamic memory operation. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. However, these control bits can, if
necessary, be altered during normal operation. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–72 shows the bit
assignments for the EMCDynamicRefresh register.
For example, for the refresh period of 16 µs, and a CCLK frequency of 50 MHz, the
following value must be programmed into this register:
(16 x 10-6 x 50 x 106) / 16 = 50 or 0x32
If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),
the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the
clock rate is reduced during the wakeup period of a reset cycle. During this period, the
EMC (and all other portions of the LPC2400 that are being clocked) run from the IRC
oscillator at 4 MHz. So, 4 MHz must be considered the CCLK rate for refresh calculations
if auto-refresh through warm reset is requested.
Note: The refresh cycles are evenly distributed. However, there might be slight variations
when the auto-refresh command is issued depending on the status of the memory
controller.
Table 72. Dynamic Memory Refresh Timer register (EMCDynamicRefresh - address
0xFFE0 8024) bit description
Bit Symbol Value Description Reset
Value
10:0 Refresh timer
(REFRESH) Indicates the multiple of 16 CCLKs between SDRAM
refresh cycles. 0
0x0 Refresh disabled (POR reset value).
0x1 0x7FF = n x16 = 16n CCLKs between SDRAM refresh
cycles.
For example:
0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh
cycles.
0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh
cycles.
31:11 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA