NXP Semiconductors LPC24XX UM10237 - Manual (Page 351)

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User manual Rev. 04 — 26 August 2009 351 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
9.6.3 USB Transmit Data register (USBTxData - 0xFFE0 C21C)
For an IN transaction, the CPU writes the endpoint data into this register. Before writing to
this register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be
set appropriately, and the packet length should be written to the USBTxPlen register. On
writing this register, the data is written to the selected endpoint buffer. The data is in little
endian format: the first byte sent on the USB bus will be the least significant byte of
USBTxData. USBTxData is a write only register.
9.6.4 USB Transmit Packet Length register (USBTxPLen - 0xFFE0 C224)
This register contains the number of bytes transferred from the CPU to the selected
endpoint buffer. Before writing data to USBTxData, software should first write the packet
length (
≤ MaxPacketSize) to this register. After each write to USBTxData, hardware
decrements USBTxPLen by 4. The WR_EN bit and LOG_ENDPOINT field of the USBCtrl
register should be set to select the desired endpoint buffer before starting this process.
For data buffers larger than the endpoint’s MaxPacketSize, software should submit data in
packets of MaxPacketSize, and send the remaining extra bytes in the last packet. For
example, if the MaxPacketSize is 64 bytes and the data buffer to be transferred is of
length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes
in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write only
register.
Table 322. USB Receive Packet Length register (USBRxPlen - address 0xFFE0 C220) bit
description
Bit Symbol Value Description Reset
value
9:0 PKT_LNGTH - The remaining number of bytes to be read from the
currently selected endpoint’s buffer. When this field
decrements to 0, the RxENDPKT bit will be set in
USBDevIntSt. 0
10 DV Data valid. This bit is useful for isochronous endpoints.
Non-isochronous endpoints do not raise an interrupt when
an erroneous data packet is received. But invalid data
packet can be produced with a bus reset. For isochronous
endpoints, data transfer will happen even if an erroneous
packet is received. In this case DV bit will not be set for the
packet. 0
0 Data is invalid.
1 Data is valid.
11 PKT_RDY - The PKT_LNGTH field is valid and the packet is ready for
reading. 0
31:12 - - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 323. USB Transmit Data register (USBTxData - address 0xFFE0 C21C) bit description
Bit Symbol Description Reset value
31:0 TX_DATA Transmit Data. 0x0000 0000