NXP Semiconductors LPC24XX UM10237 - Manual (Page 601)

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User manual Rev. 04 — 26 August 2009 601 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I 2 C interfaces I 2 C0/1/2
If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I
2 C bus stays busy indefinitely. If the STA flag is set and bus access is not
obtained within a reasonable amount of time, then a forced access to the I 2 C bus is
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I
2 C hardware behaves as if a STOP condition was received
and is able to transmit a START condition. The STO flag is cleared by hardware (see
Figure 22–125 ).
9.10 I 2 C Bus obstructed by a Low level on SCL or SDA
An I 2 C bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the
SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is
possible, and the I
2 C hardware cannot resolve this type of problem. When this occurs, the
problem must be resolved by the device that is pulling the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit
synchronization), the problem can be solved by transmitting additional clock pulses on the
SCL line (see
Figure 22–126 ). The I 2 C hardware transmits additional clock pulses when
the STA flag is set, but no START condition can be generated because the SDA line is
pulled LOW while the I
2 C bus is considered free. The I 2 C hardware attempts to generate a
START condition after every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted, state 0x08 is
entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is transmitted while SDA is
obstructed (pulled LOW), the I
2 C hardware performs the same action as described above.
In each case, state 0x08 is entered after a successful START condition is transmitted and
normal serial transfer continues. Note that the CPU is not involved in solving these bus
hang-up problems.
9.11 Bus error
A bus error occurs when a START or STOP condition is present at an illegal position in the
format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
The I 2 C hardware only reacts to a bus error when it is involved in a serial transfer either as
a master or an addressed slave. When a bus error is detected, the I 2 C block immediately
switches to the not addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 0x00. This status code may be used to
vector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in
Table 22–529 .
Fig 124. Simultaneous repeated START conditions from 2 masters
SLA A W SLA S
18H 08H
A DATA
28H 08H
OTHER MASTER
CONTINUES
other Master sends
repeated START earlier
S
retry
S P