5 non-isochronous endpoint operation – NXP Semiconductors LPC24XX UM10237 User Manual

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UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

379 of 792

NXP Semiconductors

UM10237

Chapter 13: LPC24XX USB device controller

14.4.11 LS_byte_extracted

Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of
the transfer length has been extracted. The extracted size is reflected in the
DMA_buffer_length field, bits 23:16.

14.4.12 MS_byte_extracted

Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of
the transfer size has been extracted. The size extracted is reflected in the
DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and
MS_byte_extracted bits are set.

14.4.13 Present_DMA_count

The number of bytes transferred by the DMA engine. The DMA engine updates this field
after completing each packet transfer.

For isochronous endpoints, Present_DMA_count is the number of packets transferred; for
non-isochronous endpoints, Present_DMA_count is the number of bytes.

14.4.14 Message_length_position

Used in ATLE mode. This field gives the offset of the message length position embedded
in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates
that the message length starts from the first byte of the first packet.

14.4.15 Isochronous_packetsize_memory_address

The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See

Figure 13–49

. This is applicable to

isochronous endpoints only.

14.5 Non-isochronous endpoint operation

14.5.1 Setting up DMA transfers

Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled
for DMA transfer. These DDs are present in the USB RAM. The start address of the first
DD is programmed into the DMA Description pointer (DDP) location for the corresponding
endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in
the USBEpDMAEn register (

Section 13–9.8.6

).The DMA_mode bit field in the descriptor

is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified in

Table 13–357

.

DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).

14.5.2 Finding DMA Descriptor

When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first
determine whether a new descriptor has to the fetched or not. A new descriptor does not
have to be fetched if the last packet transferred was for the same endpoint and the DD is
not yet in the retired state. An internal flag called DMA_PROCEED is used to identify this
condition (see

Section 13–14.5.4 “Optimizing descriptor fetch” on page 380

).

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