Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
Page 354
UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
354 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
[1]
DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.
9.8.2 USB DMA Request Clear register (USBDMARClr - 0xFFE0 C254)
Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt
register. Writing zero has no effect.
This register is intended for initialization prior to enabling the DMA for an endpoint. When
the DMA is enabled for an endpoint, hardware clears the corresponding bit in
USBDMARSt on completion of a packet transfer. Therefore, software should not clear the
bit using this register while the endpoint is enabled for DMA operation.
USBDMARClr is a write only register.
The USBDMARClr bit allocation is identical to the USBDMARSt register (
9.8.3 USB DMA Request Set register (USBDMARSet - 0xFFE0 C258)
Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register.
Writing zero has no effect.
This register allows software to raise a DMA request. This can be useful when switching
from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA
mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is
not raised by hardware. Software can then use this register to manually start the DMA
transfer.
Bit
15
14
13
12
11
10
9
8
Symbol
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
Bit
7
6
5
4
3
2
1
0
Symbol
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
Table 329. USB DMA Request Status register (USBDMARSt - address 0xFFE0 C250) bit description
Bit
Symbol
Value
Description
Reset value
0
EP0
0
Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0
bit must be 0).
0
1
EP1
0
Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit
must be 0).
0
31:2
EPxx
Endpoint xx (2
≤
xx
≤
31) DMA request.
0
0
DMA not requested by endpoint xx.
1
DMA requested by endpoint xx.
Table 330. USB DMA Request Clear register (USBDMARClr - address 0xFFE0 C254) bit description
Bit
Symbol
Value
Description
Reset value
0
EP0
0
Control endpoint OUT (DMA cannot be enabled for this endpoint and the
EP0 bit must be 0).
0
1
EP1
0
Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1
bit must be 0).
0
31:2
EPxx
Clear the endpoint xx (2
≤
xx
≤
31) DMA request.
0
0
No effect.
1
Clear the corresponding bit in USBDMARSt.