NXP Semiconductors LPC24XX UM10237 - Manual (Page 61)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 61 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
Sleep mode can be terminated and normal operation resumed by either a Reset or certain
specific interrupts that are able to function without clocks. Since all dynamic operation of
the chip is suspended, Sleep mode reduces chip power consumption to a very low value.
On the wakeup of sleep mode, if the IRC was used before entering sleep mode, the 2-bit
IRC timer starts counting and the code execution and peripherals activities will resume
after the timer expires (4 cycles). If the main external oscillator was used, the 12-bit main
oscillator timer starts counting and the code execution will resume when the timer expires
(4096 cycles). Customer must not forget to re-configure the PLL and clock dividers after
the wakeup.
3.4.3 Power-down mode
Power-down mode does everything that Sleep mode does, but also turns off the flash
memory. This saves more power, but requires waiting for resumption of flash operation
before execution of code or data access in the flash memory can be accomplished.
When the chip enters power-down mode, the IRC, the main oscillator and all clocks are
stopped. The 32Khz RTC oscillator is not stopped because the RTC interrupts may be
used as the wakeup source. The flash is forced into power-down mode. The PLL is
automatically turned off and disconnected. The CCLK and USBCLK clock dividers
automatically get reset to zero.
On the wakeup of power-down mode, if the IRC was used before entering power-down
mode, after IRC-start-up time (60
μs), the 2-bit IRC timer starts counting and expires in 4
cycles. The code execution can then be resumed immediately upon the expiration of the
IRC timer if the code was running from SRAM. In the meantime, the flash wakeup-timer
generates flash start-up time 100
μs. When it times out, access to the flash is enabled.
Customer must not forget to re-configure the PLL and clock dividers after the wakeup.
3.4.4 Deep power-down mode
Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies
power to internal logic is also shut off. This produces the lowest possible power
consumption without actually removing power from the entire chip. Since Deep
power-down mode shuts down the on-chip logic power supply, there is no register or
memory retention, and resumption of operation involves the same activities as a full-chip
reset.
If power is supplied to the LPC2400 during Deep power-down mode, wakeup can be
caused by the RTC alarm or external reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2400 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the battery RAM, as long as the external power
to the VBAT pin is maintained.