Descriptor and status formats, 1 receive descriptors and statuses, Own in – NXP Semiconductors LPC24XX UM10237 User Manual

Page 241: Table 11–231, Nxp semiconductors

Advertising
background image

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

241 of 792

NXP Semiconductors

UM10237

Chapter 11: LPC24XX Ethernet

The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the
corresponding bit in the status register. Writing a 0 will not affect the interrupt status.

7.4.5 Power-Down Register (PowerDown - 0xFFE0 0FF4)

The Power-Down register (PowerDown) is used to block all AHB accesses except
accesses to the PowerDown register. The register has an address of 0xFFE0 0FF4. The
bit definition of the register is listed in

Table 11–232

.

Setting the bit will return an error on all read and write accesses on the MACAHB interface
except for accesses to the PowerDown register.

8.

Descriptor and status formats

This section defines the descriptor format for the transmit and receive scatter/gather DMA
engines. Each Ethernet frame can consist of one or more fragments. Each fragment
corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for
receive) and gather (for transmit) multiple fragments for a single Ethernet frame.

8.1 Receive descriptors and statuses

Figure 11–28

depicts the layout of the receive descriptors in memory.

Table 231. Interrupt Set register (IntSet - address 0xFFE0 0FEC) bit description

Bit

Symbol

Function

Reset
value

0

RxOverrunIntSet

Writing a ’1’ to one of these bits (0 to 7) sets the
corresponding status bit in interrupt status register
IntStatus.

0

1

RxErrorIntSet

0

2

RxFinishedIntSet

0

3

RxDoneIntSet

0

4

TxUnderrunIntSet

0

5

TxErrorIntSet

0

6

TxFinishedIntSet

0

7

TxDoneIntSet

0

11:8

-

Unused

0x0

12

SoftIntSet

Writing a ’1’ to one of these bits (12 and/or 13) sets the
corresponding status bit in interrupt status register
IntStatus.

0

13

WakeupIntSet

0

31:14

-

Unused

0x0

Table 232. Power-Down register (PowerDown - address 0xFFE0 0FF4) bit description

Bit

Symbol

Function

Reset
value

30:0

-

Unused

0x0

31

PowerDownMACAHB

If true, all AHB accesses will return a read/write error,
except accesses to the PowerDown register.

0

Advertising