Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

Page 768

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UM10237_4

User manual

Rev. 04 — 26 August 2009

768 of 792

NXP Semiconductors

UM10237

Chapter 36: LPC24XX Supplementary information

address 0xE001 0004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .448

Table 402.UART1 Interrupt Identification Register (U1IIR -

address 0xE001 0008, Read Only) bit description
449

Table 403.UART1 Interrupt Handling . . . . . . . . . . . . . . .451
Table 404.UART1 FIFO Control Register (U1FCR - address

0xE001 0008, Write Only) bit description . . . .452

Table 405.UART1 Line Control Register (U1LCR - address

0xE001 000C) bit description . . . . . . . . . . . . .452

Table 406.UART1 Modem Control Register (U1MCR -

address 0xE001 0010) bit description . . . . . .453

Table 407.Modem status interrupt generation . . . . . . . . .455
Table 408.UART1 Line Status Register (U1LSR - address

0xE001 0014, Read Only) bit description . . . .456

Table 409.UART1 Modem Status Register (U1MSR -

address 0xE001 0018) bit description . . . . . .457

Table 410.UART1 Scratch Pad Register (U1SCR - address

0xE001 0014) bit description . . . . . . . . . . . . .458

Table 411. Auto-baud Control Register (U1ACR - address

0xE001 0020) bit description . . . . . . . . . . . . .458

Table 412.UART1 Fractional Divider Register (U1FDR -

address 0xE001 0028) bit description . . . . . .462

Table 413.Fractional Divider setting look-up table. . . . . .464
Table 414.UART1 Transmit Enable Register (U1TER -

address 0xE001 0030) bit description . . . . . .465

Table 415.CAN Pin descriptions . . . . . . . . . . . . . . . . . . .468
Table 416.Memory map of the CAN block. . . . . . . . . . . .473
Table 417.Summary of CAN acceptance filter and central

CAN registers . . . . . . . . . . . . . . . . . . . . . . . . .473

Table 418.Summary of CAN1 and CAN2 controller

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473

Table 419.Access to CAN1 and CAN2 controller

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474

Table 420. Mode register (CAN1MOD - address

0xE004 4000, CAN2MOD - address
0xE004 8000) bit description . . . . . . . . . . . . .475

Table 421.Command Register (CAN1CMR - address

0xE004 4004, CAN2CMR - address
0xE004 8004) bit description . . . . . . . . . . . . .477

Table 422. Global Status Register (CAN1GSR - address

0xE004 4008, CAN2GSR - address
0xE004 8008) bit description . . . . . . . . . . . . .478

Table 423.Interrupt and Capture Register (CAN1ICR -

address 0xE004 400C, CAN2ICR - address
0xE004 800C) bit description . . . . . . . . . . . . .481

Table 424.Interrupt Enable Register (CAN1IER - address

0xE004 4010, CAN2IER - address 0xE004 8010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .485

Table 425. Bus Timing Register (CAN1BTR - address

0xE004 4014, CAN2BTR - address 0xE004 8014)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .486

Table 426.Error Warning Limit register (CAN1EWL - address

0xE004 4018, CAN2EWL - address
0xE004 8018) bit description . . . . . . . . . . . . .487

Table 427. Status Register (CAN1SR - address

0xE004 401C, CAN2SR - address 0xE004 801C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .487

Table 428.Receive Frame Status register (CAN1RFS -

address 0xE004 4020, CAN2RFS - address
0xE004 8020) bit description . . . . . . . . . . . . . 489

Table 429.Receive Identifier Register (CAN1RID - address

0xE004 4024, CAN2RID - address 0xE004 8024)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 490

Table 430.RX Identifier register when FF = 1 . . . . . . . . . 490
Table 431.Receive Data register A (CAN1RDA - address

0xE004 4028, CAN2RDA - address
0xE004 8028) bit description . . . . . . . . . . . . . 490

Table 432.Receive Data register B (CAN1RDB - address

0xE004 402C, CAN2RDB - address
0xE004 802C) bit description. . . . . . . . . . . . . 491

Table 433.Transmit Frame Information Register

(CAN1TFI[1/2/3] - address 0xE004 40[30/40/50],
CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

Table 434.Transfer Identifier Register (CAN1TID[1/2/3] -

address 0xE004 40[34/44/54], CAN2TID[1/2/3] -
address 0xE004 80[34/44/54]) bit description 493

Table 435.Transfer Identifier register when FF = 1 . . . . . 493
Table 436.Transmit Data Register A (CAN1TDA[1/2/3] -

address 0xE004 40[38/48/58], CAN2TDA[1/2/3] -
address 0xE004 80[38/48/58]) bit description 493

Table 437.Transmit Data Register B (CAN1TDB[1/2/3] -

address 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3]
- address 0xE004 80[3C/4C/5C]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Table 438.Central Transit Status Register (CANTxSR -

address 0xE004 0000) bit description . . . . . . 495

Table 439.Central Receive Status Register (CANRxSR -

address 0xE004 0004) bit description . . . . . . 496

Table 440.Central Miscellaneous Status Register (CANMSR

- address 0xE004 0008) bit description . . . . . 496

Table 441.Acceptance filter modes and access control . 497
Table 442.Section configuration register settings . . . . . . 498
Table 443.Acceptance Filter Mode Register (AFMR -

address 0xE003 C000) bit description . . . . . . 501

Table 444.Standard Frame Individual Start Address Register

(SFF_sa - address 0xE003 C004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Table 445.Standard Frame Group Start Address Register

(SFF_GRP_sa - address 0xE003 C008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

Table 446.Extended Frame Start Address Register (EFF_sa

- address 0xE003 C00C) bit description . . . . 503

Table 447.Extended Frame Group Start Address Register

(EFF_GRP_sa - address 0xE003 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 503