NXP Semiconductors LPC24XX UM10237 - Manual (Page 361)

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User manual Rev. 04 — 26 August 2009 361 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
register to request low priority interrupt handling. However, the USBDevIntPri register can
route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt
register.
Only one of the EP_FAST and FRAME interrupt events can be routed to the
USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both
interrupt events are routed to USB_INT_REQ_LP.
Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for
low priority interrupt handling by software.
The final interrupt signal to the VIC is gated by the EN_USB_INTS bit in the USBIntSt
register. The USB interrupts are routed to VIC channel #22 only if EN_USB_INTS is set.
DMA mode
If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not
enabled in the USBEpIntEn register, the corresponding status bit in the USBDMARSt is
set by hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer
is enabled for the corresponding endpoint in the USBEpDMASt register.
Three types of interrupts can occur for each endpoint for data transfers in DMA mode: End
of transfer interrupt , new DD request interrupt, and system error interrupt. These interrupt
events set a bit for each endpoint in the respective registers USBEoTIntSt,
USBNDDRIntSt, and USBSysErrIntSt. The End of transfer interrupts from all endpoints
are then Ored and routed to the EOT bit in USBDMAIntSt. Likewise, all New DD request
interrupts and system error interrupt events are routed to the NDDR and ERR bits
respectively in the USBDMAStInt register.
The EOT, NDDR, and ERR bits (if enabled in USBDMAIntEn) are ORed to set the
USB_INT_REQ_DMA bit in the USBIntSt register. If the EN_USB_INTS bit is set in
USBIntSt, the interrupt is routed to VIC channel #22.