NXP Semiconductors LPC24XX UM10237 - Manual (Page 790)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 790 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 676
5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
5.1 Memory map after any reset. . . . . . . . . . . . . 677
5.1.1 Criterion for Valid User Code . . . . . . . . . . . . 677
5.2 Communication protocol . . . . . . . . . . . . . . . . 678
5.2.1 ISP command format . . . . . . . . . . . . . . . . . . 678
5.2.2 ISP response format . . . . . . . . . . . . . . . . . . . 678
5.2.3 ISP data format. . . . . . . . . . . . . . . . . . . . . . . 678
5.2.4 ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 679
5.2.5 ISP command abort . . . . . . . . . . . . . . . . . . . 679
5.2.6 Interrupts during ISP. . . . . . . . . . . . . . . . . . . 679
5.2.7 Interrupts during IAP. . . . . . . . . . . . . . . . . . . 679
5.2.8 RAM used by ISP command handler . . . . . . 679
5.2.9 RAM used by IAP command handler . . . . . . 679
5.2.10 RAM used by RealMonitor . . . . . . . . . . . . . . 679
6 Boot process flowchart . . . . . . . . . . . . . . . . . 680
7 Sector numbers . . . . . . . . . . . . . . . . . . . . . . . 681
8 Code Read Protection (CRP) . . . . . . . . . . . . 682
9 ISP commands . . . . . . . . . . . . . . . . . . . . . . . . 683
9.1 Unlock <Unlock code> . . . . . . . . . . . . . . . . . 684
9.2 Set Baud Rate <Baud Rate> <stop bit> . . . . 684
9.3 Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 685
9.4 Write to RAM <start address> <number of
bytes> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
9.5 Read Memory <address> <no. of bytes> . . . 685
9.6 Prepare sector(s) for write operation <start sector
number> <end sector number> . . . . . . . . . . 686
9.7 Copy RAM to Flash <Flash address> <RAM
address> <no of bytes> . . . . . . . . . . . . . . . . 687
9.8 Go <address> <mode> . . . . . . . . . . . . . . . . 687
9.9 Erase sector(s) <start sector number> <end
sector number> . . . . . . . . . . . . . . . . . . . . . . 688
9.10 Blank check sector(s) <sector number> <end
sector number> . . . . . . . . . . . . . . . . . . . . . . 688
9.11 Read Part Identification number . . . . . . . . . 688
9.12 Read Boot code version number . . . . . . . . . 689
9.13 Compare <address1> <address2>
<no of bytes> . . . . . . . . . . . . . . . . . . . . . . . . 689
9.14 ISP Return Codes . . . . . . . . . . . . . . . . . . . . 690
10 IAP commands . . . . . . . . . . . . . . . . . . . . . . . 690
10.1 Prepare sector(s) for write operation . . . . . . 692
10.2 Copy RAM to Flash . . . . . . . . . . . . . . . . . . . 693
10.3 Erase Sector(s) . . . . . . . . . . . . . . . . . . . . . . 694
10.4 Blank check sector(s). . . . . . . . . . . . . . . . . . 694
10.5 Read Part Identification number . . . . . . . . . 694
10.6 Read Boot code version number . . . . . . . . . 695
10.7 Compare <address1> <address2>
<no of bytes> . . . . . . . . . . . . . . . . . . . . . . . . 695
10.8 Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . 695
10.9 IAP Status Codes . . . . . . . . . . . . . . . . . . . . . 696
11 JTAG Flash programming interface . . . . . . 696
Chapter 31: LPC24XX On-chip bootloader for flashless parts
1 How to read this chapter . . . . . . . . . . . . . . . . 697
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 697
4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
4.1 Memory map after any reset. . . . . . . . . . . . . 698
4.2 Communication protocol . . . . . . . . . . . . . . . . 698
4.2.1 ISP command format . . . . . . . . . . . . . . . . . . 699
4.2.2 ISP response format . . . . . . . . . . . . . . . . . . . 699
4.2.3 ISP data format. . . . . . . . . . . . . . . . . . . . . . . 699
4.2.4 ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 699
4.2.5 ISP command abort . . . . . . . . . . . . . . . . . . . 699
4.2.6 Interrupts during ISP. . . . . . . . . . . . . . . . . . . 699
4.2.7 Interrupts during IAP. . . . . . . . . . . . . . . . . . . 699
4.2.8 RAM used by ISP command handler . . . . . . 699
4.2.9 RAM used by IAP command handler . . . . . . 700
4.2.10 RAM used by RealMonitor . . . . . . . . . . . . . . 700
5 Boot process flowchart . . . . . . . . . . . . . . . . . 700
6 ISP commands . . . . . . . . . . . . . . . . . . . . . . . . 701
6.1 Unlock <Unlock code> . . . . . . . . . . . . . . . . . 701
6.2 Set Baud Rate <Baud Rate> <stop bit>. . . . 701
6.3 Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 702
6.4 Write to RAM <start address>
<number of bytes> . . . . . . . . . . . . . . . . . . . . 702
6.5 Read Memory <address> <no. of bytes>. . . 703
6.6 Go <address> <mode> . . . . . . . . . . . . . . . . 704
6.7 Read Part Identification number . . . . . . . . . 704
6.8 Read Boot code version number . . . . . . . . . 704
6.9 Compare <address1> <address2>
<no of bytes> . . . . . . . . . . . . . . . . . . . . . . . . 705
6.10 ISP Return Codes . . . . . . . . . . . . . . . . . . . . 705
7 IAP commands . . . . . . . . . . . . . . . . . . . . . . . 706
7.1 Read Part Identification number . . . . . . . . . 708
7.2 Read Boot code version number . . . . . . . . . 708
7.3 Compare <address1> <address2>
<no of bytes> . . . . . . . . . . . . . . . . . . . . . . . . 709
7.4 Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . 709
7.5 IAP Status Codes . . . . . . . . . . . . . . . . . . . . . 709
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
1 Basic configuration . . . . . . . . . . . . . . . . . . . . 711
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 711
3 Features of the GPDMA. . . . . . . . . . . . . . . . . 711
4 Functional overview . . . . . . . . . . . . . . . . . . . 712
4.1 Memory regions accessible by the GPDMA . 712
4.2 GPDMA functional description . . . . . . . . . . . 712
4.2.1 AHB Slave Interface. . . . . . . . . . . . . . . . . . . 713
4.2.2 Control Logic and Register Bank . . . . . . . . . 713
4.2.3 DMA Request and Response Interface . . . . 713
4.2.4 Channel Logic and Channel Register Bank . 714
4.2.5 Interrupt Request . . . . . . . . . . . . . . . . . . . . . 714
4.2.6 AHB Master Interface. . . . . . . . . . . . . . . . . . 714
4.2.7 Bus and transfer widths . . . . . . . . . . . . . . . . 714