NXP Semiconductors LPC24XX UM10237 - Manual (Page 570)

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User manual Rev. 04 — 26 August 2009 570 of 792
NXP Semiconductors
UM10237
Chapter 21: LPC24XX SD/MMC card interface
6.12 Clear Register (MCIClear - 0xE008 C038)
The MCIClear register is a write-only register. The corresponding static status flags can be
cleared by writing a 1 to the corresponding bit in the register.
Table 21–505 shows the bit
assignment of the MCIClear register.
6.13 Interrupt Mask Registers (MCIMask0 - 0xE008 C03C)
The interrupt mask registers determine which status flags generate an interrupt request by
setting the corresponding bit to 1.
Table 21–506 shows the bit assignment of the
MCIMaskx registers.
20 TxDataAvlbl Data available in transmit FIFO. 0
21 RxDataAvlbl Data available in receive FIFO. 0
31:22 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 504: Status register (MCIStatus - address 0xE008 C034) bit description
Bit Symbol Description Reset
Value
Table 505: Clear register (MCIClear - address 0xE008 C038) bit description
Bit Symbol Description Reset
Value
0 CmdCrcFailClr Clears CmdCrcFail flag. -
1 DataCrcFailClr Clears DataCrcFail flag. -
2 CmdTimeOutClr Clears CmdTimeOut flag. -
3 DataTimeOutClr Clears DataTimeOut flag. -
4 TxUnderrunClr Clears TxUnderrun flag. -
5 RxOverrunClr Clears RxOverrun flag. -
6 CmdRespEndClr Clears CmdRespEnd flag. -
7 CmdSentClr Clears CmdSent flag. -
8 DataEndClr Clears DataEnd flag. -
9 StartBitErrClr Clears StartBitErr flag. -
10 DataBlockEndClr Clears DataBlockEnd flag. -
31:11 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 506: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C) bit description
Bit Symbol Description Reset
Value
0 Mask0 Mask CmdCrcFail flag. 0
1 Mask1 Mask DataCrcFail flag. 0
2 Mask2 Mask CmdTimeOut flag. 0
3 Mask3 Mask DataTimeOut flag. 0
4 Mask4 Mask TxUnderrun flag. 0
5 Mask5 Mask RxOverrun flag. 0
6 Mask6 Mask CmdRespEnd flag. 0
7 Mask7 Mask CmdSent flag. 0