NXP Semiconductors LPC24XX UM10237 - Manual (Page 58)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 58 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
3.3.2 USB Clock Configuration register (USBCLKCFG - 0xE01F C108)
The USBCLKCFG register controls the division of the PLL output before it is used by the
USB block. If the PLL is bypassed, the division may be by 1. In that case, the PLL input
frequency must be 48 MHz, with a 500 ppm tolerance. When the PLL is running, the
output must be divided in order to bring the USB clock frequency to 48 MHz with a 50%
duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of
48 MHz (i.e. any mutliple of 96 MHz) within the PLL operating range.
Remark: The Internal RC clock can not be used as a clock source for USB because a
more precise clock is needed (see
Table 4–42 ).
[1] Actual reset value depends on IRC factory trimming.
The USB clock is derived from the PLL output signal, divided by USBSEL + 1. Having
USBSEL = 1 results in USB’s clock being one half the PLL output.
3.3.3 IRC Trim Register (IRCTRIM - 0xE01F C1A4)
This register is used to trim the on-chip 4 MHz oscillator.
3.3.4 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0xE01F C1A8 and
PCLKSEL1 - 0xE01F C1AC)
A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal
that will be supplied to the corresponding peripheral as specified in
Table 4–56 ,
Table 4–57 and Table 4–58 .
Table 54. USB Clock Configuration register (USBCLKCFG - address 0xE01F C108) bit
description
Bit Symbol Description Reset
value
3:0 USBSEL Selects the divide value for creating the USB clock from the PLL output.
Warning: Improper setting of this value will result in incorrect operation
of the USB interface.
0
7:4 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
Table 55. IRC Trim register (IRCTRIM - address 0xE01F C1A4) bit description
Bit Symbol Description Reset
value
7:0 IRCtrim IRC trim value. It controls the on-chip 4 MHz IRC frequency. 0xA0
15:8 - Reserved. Software must write 0 into these bits. NA
Table 56. Peripheral Clock Selection register 0 (PCLKSEL0 - address 0xE01F C1A8) bit
description
Bit Symbol Description Reset
value
1:0 PCLK_WDT Peripheral clock selection for WDT. 00
3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00
5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00
7:6 PCLK_UART0 Peripheral clock selection for UART0. 00
9:8 PCLK_UART1 Peripheral clock selection for UART1. 00