NXP Semiconductors LPC24XX UM10237 - Manual (Page 373)

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User manual Rev. 04 — 26 August 2009 373 of 792
NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and
USBSysErrIntClr.
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0
0000).
– Enable the desired endpoints for DMA operation using USBEpDMAEn.
– Set EOT, DDR, and ERR bits in USBDMAIntEn.
10. Install USB interrupt handler in the VIC by writing its address to the corresponding
VICVectAddr register and enabling the USB interrupt in the VICIntEnable register.
11. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address
command. A bus reset will also cause this to happen.
12. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status
command.
The configuration of the endpoints varies depending on the software application. By
default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional
endpoints are enabled and configured by software after a SET_CONFIGURATION or
SET_INTERFACE device request is received from the host.
13. Slave mode operation
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface.
13.1 Interrupt generation
In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated
in response to an endpoint interrupt. Endpoint interrupts are enabled using the
USBEpIntEn register, and are observable in the USBEpIntSt register.
All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a
packet without an error. All non-isochronous IN endpoints generate an interrupt when a
packet is successfully transmitted, or when a NAK handshake is sent on the bus and the
interrupt on NAK feature is enabled.
For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in
USBDevIntSt) occurs.
13.2 Data transfer for OUT endpoints
When the software wants to read the data from an endpoint buffer it should set the
RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the
USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register,
and set the PKT_RDY bit (
Table 13–322 ).
Software can now start reading the data from the USBRxData register ( Table 13–321 ).
When the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is
set in the USBDevSt register. Software now issues a Clear Buffer (refer to
Table 13–356 )
command. The endpoint is now ready to accept the next packet. For OUT isochronous