NXP Semiconductors LPC24XX UM10237 - Manual (Page 658)

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User manual Rev. 04 — 26 August 2009 658 of 792
NXP Semiconductors
UM10237
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
pulses, this "jitter" could possibly be of concern in an application that wishes to observe
the contents of the Clock Tick Counter (CTC) directly(
Section 26–6.2.2 “Clock Tick
Counter Register (CTCR - 0xE002 4004)” on page 651 ).
6.7.5 Prescaler operation
The Prescaler block labelled "Combination Logic" in Figure 26–135 determines when the
decrement of the 13 bit PREINT counter is extended by one PCLK. In order to both insert
the correct number of longer cycles, and to distribute them evenly, the combinatorial Logic
associates each bit in PREFRAC with a combination in the 15 bit Fraction Counter. These
associations are shown in the following
Table 26–582 .
For example, if PREFRAC bit 14 is a one (representing the fraction 1/2), then half of the
cycles counted by the 13 bit counter need to be longer. When there is a 1 in the LSB of the
Fraction Counter, the logic causes every alternate count (whenever the LSB of the
Fraction Counter=1) to be extended by one PCLK, evenly distributing the pulse widths.
Similarly, a one in PREFRAC bit 13 (representing the fraction 1/4) will cause every fourth
cycle (whenever the two LSBs of the Fraction Counter = 10) counted by the 13 bit counter
to be longer.
Fig 135. RTC prescaler block diagram
to clock tick counter
13 BIT INTEGER COUNTER
(DOWN COUNTER)
15 BIT FRACTION COUNTER
COMBINATORIAL LOGIC
15 BIT FRACTION REGISTER
(PREFRAC)
15
15
15
13 BIT RELOAD INTEGER
REGISTER
(PREINT)
13
13
APB bus
PCLK
(APB clock)
CLK
CLK
RELOAD
UNDERFLOW
extend
reload