NXP Semiconductors LPC24XX UM10237 - Manual (Page 315)

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User manual Rev. 04 — 26 August 2009 315 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
7.11 Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024)
The LCD_INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the
LCD_INTRAW register and the LCD_INTMASK register. A logical OR of all interrupts is
provided to the system interrupt controller.
The contents of LCD_INTSTAT register are described in Table 12–270 .
7.12 Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028)
The LCD_INTCLR register is Write-Only. Writing a logic 1 to the relevant bit clears the
corresponding interrupt.
The contents of the LCD_INTCLR register are described in Table 12–271 .
Table 270. Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024)
Bits Function Description Reset
value
31:5 reserved Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
4 BERMIS AHB master bus error masked interrupt status.
Set when the both the BERRAW bit in the LCD_INTRAW
register and the BERIM bit in the LCD_INTMSK register are set.
0x0
3 VCompMIS Vertical compare masked interrupt status.
Set when the both the VCompRIS bit in the LCD_INTRAW
register and the VCompIM bit in the LCD_INTMSK register are
set.
0x0
2 LNBUMIS LCD next address base update masked interrupt status.
Set when the both the LNBURIS bit in the LCD_INTRAW
register and the LNBUIM bit in the LCD_INTMSK register are
set.
0x0
1 FUFMIS FIFO underflow masked interrupt status.
Set when the both the FUFRIS bit in the LCD_INTRAW register
and the FUFIM bit in the LCD_INTMSK register are set.
0x0
0 reserved Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
Table 271. Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028)
Bits Function Description Reset
value
31:5 reserved Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
4 BERIC AHB master error interrupt clear.
Writing a 1 to this bit clears the AHB master error interrupt.
0x0
3 VCompIC Vertical compare interrupt clear.
Writing a 1 to this bit clears the vertical compare interrupt.
0x0