Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

Page 35

Advertising
background image

UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

35 of 792

NXP Semiconductors

UM10237

Chapter 3: LPC24XX System control

[1]

Allowed values for nnn are: 101 (highest priority), 100, 011, 010, 001 (lowest priority).

Table 30.

AHB Arbiter Configuration register 1 (AHBCFG1 - address 0xE01F C188) bit
description

Bit

Symbol

Value Description

Reset
value

0

scheduler

0

Priority scheduling.

1

1

Uniform (round-robin) scheduling.

2:1

break_burst

00

Break all defined length bursts (the CPU does not create
defined bursts).

10

01

Break all defined length bursts greater than four-beat.

10

Break all defined length bursts greater than eight-beat.

11

Never break defined length bursts.

3

quantum_type

0

A quantum is an AHB clock.

0

1

A quantum is an AHB bus cycle.

7:4

quantum_size

Controls the type of arbitration and the number of quanta
before re-arbiration occurs.

0100

0000

Preemptive, re-arbitrate after 1 AHB quantum.

0001

Preemptive, re-arbitrate after 2 AHB quanta.

0010

Preemptive, re-arbitrate after 4 AHB quanta.

0011

Preemptive, re-arbitrate after 8 AHB quanta.

0100

Preemptive, re-arbitrate after 16 AHB quanta.

0101

Preemptive, re-arbitrate after 32 AHB quanta.

0110

Preemptive, re-arbitrate after 64 AHB quanta.

0111

Preemptive, re-arbitrate after 128 AHB quanta.

1000

Preemptive, re-arbitrate after 256 AHB quanta.

1001

Preemptive, re-arbitrate after 512 AHB quanta.

1010

Preemptive, re-arbitrate after 1024 AHB quanta.

1011

Preemptive, re-arbitrate after 2048 AHB quanta.

1100

Preemptive, re-arbitrate after 4096 AHB quanta.

1101

Preemptive, re-arbitrate after 8192 AHB quanta.

1110

Preemptive, re-arbitrate after 16384 AHB quanta.

1111

Non- preemptive, infinite AHB quanta.

10:8

default_master

nnn

[1]

Master 1 (CPU) is the default master.

001

11

-

-

Reserved.

-

14:12 EP1

nnn

[1]

External priority for master 1 (CPU).

000

15

-

-

Reserved.

-

18:16 EP2

nnn

[1]

External priority for master 2 (GPDMA).

000

19

-

-

Reserved.

-

22:20 EP3

nnn

[1]

External priority for master 3 (AHB1).

000

23

-

-

Reserved.

-

26:24 EP4

nnn

[1]

External priority for master 4 (USB).

000

27

-

--

Reserved.

-

30:28 EP5

nnn

[1]

External priority for master 5 (LCD).

000

31

-

-

Reserved.

-

Advertising