NXP Semiconductors LPC24XX UM10237 - Manual (Page 638)

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User manual Rev. 04 — 26 August 2009 638 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Table 557. PWM0 and PWM1 register map
Generic
Name Description Access Reset
Value [1]
PWM0 Address
& Name PWM1 Address
& Name
IR Interrupt Register. The IR can be written to clear
interrupts. The IR can be read to identify which of eight
possible interrupt sources are pending. R/W 0 0xE001 4000
PWM0IR 0xE001 8000
PWM1IR
TCR Timer Control Register. The TCR is used to control the
Timer Counter functions. The Timer Counter can be
disabled or reset through the TCR. R/W 0 0xE001 4004
PWM0TCR 0xE001 8004
PWM1TCR
TC Timer Counter. The 32 bit TC is incremented every PR+1
cycles of PCLK. The TC is controlled through the TCR. R/W 0 0xE001 4008
PWM0TC 0xE001 8008
PWM1TC
PR Prescale Register. The TC is incremented every PR+1
cycles of PCLK. R/W 0 0xE001 400C
PWM0PR 0xE001 800C
PWM1PR
PC Prescale Counter. The 32 bit PC is a counter which is
incremented to the value stored in PR. When the value in
PR is reached, the TC is incremented. The PC is
observable and controllable through the bus interface. R/W 0 0xE000 4010
PWM0PC 0xE001 8010
PWM1PC
MCR Match Control Register. The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match
occurs. R/W 0 0xE001 4014
PWM0MCR 0xE001 8014
PWM0MCR
MR0 Match Register 0. MR0 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC sets any PWM output that
is in single-edge mode, and sets PWM1 if it’s in
double-edge mode. R/W 0 0xE001 4018
PWM0MR0 0xE001 8018
PWM1MR0
MR1 Match Register 1. MR1 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM1 in either
edge mode, and sets PWM2 if it’s in double-edge mode. R/W 0 0xE001 401C
PWM0MR1 0xE001 801C
PWM1MR1
MR2 Match Register 2. MR2 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM2 in either
edge mode, and sets PWM3 if it’s in double-edge mode. R/W 0 0xE001 4020
PWM0MR2 0xE001 8020
PWM1MR2
MR3 Match Register 3. MR3 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM3 in either
edge mode, and sets PWM4 if it’s in double-edge mode. R/W 0 0xE001 4024
PWM0MR3 0xE001 8024
PWM1MR3
CCR Capture Control Register. The CCR controls which edges
of the capture inputs are used to load the Capture
Registers and whether or not an interrupt is generated
when a capture takes place. R/W 0 0xE001 4028
PWM0CCR 0xE001 8028
PWM1CCR
CR0 Capture Register 0. PWMn CR0 is loaded with the value
of the TC when there is an event on the CAPn.0 input. RO 0 0xE001 402C
PWM0CR0 -
CR1 Capture Register 1. See CR0 description. RO 0 0xE001 4030
PWM0CR1 0xE001 8030
PWM1CR1