NXP Semiconductors LPC24XX UM10237 - Manual (Page 201)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 201 of 792
NXP Semiconductors
UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Legacy registers are the IO0SET and IO1SET while the enhanced GPIOs are supported
via the FIO0SET, FIO1SET, FIO2SET, FIO3SET, and FIO4SET registers. Access to a port
pin via the FIOSET register is conditioned by the corresponding bit of the FIOMASK
register (see
Section 10–6.5 “Fast GPIO port Mask register
FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)” ).
Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 10–166 , too. Next to providing the same functions as the FIOSET register, these
additional registers allow easier and faster access to the physical port pins.
Table 164. GPIO port output Set register (IO0SET - address 0xE002 8004 and IO1SET -
address 0xE002 8014) bit description
Bit Symbol Value Description Reset
value
31:0 P0xSET
or
P1xSET
0
Slow GPIO output value Set bits. Bit 0 in IOxSET controls pin
Px.0, bit 31 in IOxSET controls pin Px.31.
Controlled pin output is unchanged.
0x0
1 Controlled pin output is set to HIGH.
Table 165. Fast GPIO port output Set register (FIO[0/1/2/3/4]SET - address
0x3FFF C0[1/3/5/7/9]8) bit description
Bit Symbol Value Description Reset
value
31:0 FP0xSET
FP1xSET
FP2xSET
FP3xSET
FP4xSET
0
Fast GPIO output value Set bits. Bit 0 in FIOxSET controls pin
Px.0, bit 31 in FIOxSET controls pin Px.31.
Controlled pin output is unchanged.
0x0
1 Controlled pin output is set to HIGH.
Table 166. Fast GPIO port output Set byte and half-word accessible register description
Generic
Register
name Description Register
length (bits)
& access Reset
value PORTn Register
Address & Name
FIOxSET0 Fast GPIO Port x output Set
register 0. Bit 0 in FIOxSET0
register corresponds to pin
Px.0 ... bit 7 to pin Px.7. 8 (byte)
R/W 0x00 FIO0SET0 - 0x3FFF C018
FIO1SET0 - 0x3FFF C038
FIO2SET0 - 0x3FFF C058
FIO3SET0 - 0x3FFF C078
FIO4SET0 - 0x3FFF C098
FIOxSET1 Fast GPIO Port x output Set
register 1. Bit 0 in FIOxSET1
register corresponds to pin
Px.8 ... bit 7 to pin Px.15. 8 (byte)
R/W 0x00 FIO0SET1 - 0x3FFF C019
FIO1SET1 - 0x3FFF C039
FIO2SET1 - 0x3FFF C059
FIO3SET1 - 0x3FFF C079
FIO4SET1 - 0x3FFF C099
FIOxSET2 Fast GPIO Port x output Set
register 2. Bit 0 in FIOxSET2
register corresponds to pin
Px.16 ... bit 7 to pin Px.23. 8 (byte)
R/W 0x00 FIO0SET2 - 0x3FFF C01A
FIO1SET2 - 0x3FFF C03A
FIO2SET2 - 0x3FFF C05A
FIO3SET2 - 0x3FFF C07A
FIO4SET2 - 0x3FFF C09A