1 memory map after any reset, Section 30–5.1.1, Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

Page 677: 1 criterion for valid user code

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UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

677 of 792

NXP Semiconductors

UM10237

Chapter 30: LPC24XX Flash memory programming firmware

When ISP mode is entered after a power on reset, the IRC and PLL are used to generate
CCLK of 14.748 MHz. This may not be the case when ISP is invoked by the user
application (see

Section 30–10.8 “Reinvoke ISP” on page 695

).

5.1 Memory map after any reset

The Flash portion of the boot block is 8 kB in size and resides in the top portion (starting
from 0x0007 E000) of the on-chip Flash memory. After any reset the entire boot block is
also mapped to the top of the on-chip memory space i.e. the boot block is also visible in
the memory region starting from the address 0x7FFF E000. The Flash boot loader is
designed to run from this memory area, but both the ISP and IAP software use parts of the
on-chip RAM. The RAM usage is described later in this chapter. The interrupt vectors
residing in the boot block of the on-chip Flash memory also become active after reset, i.e.,
the bottom 64 bytes of the boot block are also visible in the memory region starting from
the address 0x0000 0000. The reset vector contains a jump instruction to the entry point
of the flash boot loader software.

5.1.1 Criterion for Valid User Code

Criterion for valid user code: The reserved ARM interrupt vector location (0x0000 0014)
should contain the 2’s complement of the check-sum of the remaining interrupt vectors.
This causes the checksum of all of the vectors together to be 0. The boot loader code
disables the overlaying of the interrupt vectors from the boot block, then checksums the
interrupt vectors in sector 0 of the Flash. If the signatures match then the execution
control is transferred to the user code by loading the program counter with 0x0000 0000.
Hence the user Flash reset vector should contain a jump instruction to the entry point of
the user application code.

Fig 138. Map of lower memory after reset

8 kB BOOT BLOCK

(RE-MAPPED FROM TOP OF FLASH MEMORY)

ON-CHIP FLASH MEMORY

0.0 GB

ACTIVE INTERRUPT VECTORS

FROM THE BOOT BLOCK

0x7FFF FFFF

2.0 GB - 8 kB

2.0 GB

(BOOT BLOCK INTERRUPT VECTORS)

8 kB BOOT BLOCK RE-MAPPED TO

HIGHER ADDRESS RANGE

0x0000 0000

0x0007 FFFF

0x7FFF E000

0x0007 E000

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