NXP Semiconductors LPC24XX UM10237 - Manual (Page 631)

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User manual Rev. 04 — 26 August 2009 631 of 792
NXP Semiconductors
UM10237
Chapter 24: LPC24XX Timer0/1/2/3
Fig 131. Timer block diagram
reset MAXVAL
TIMER CONTROL REGISTER PRESCALE REGISTER
PRESCALE COUNTER
PCLK
enable
CAPTURE REGISTER 3
CAPTURE REGISTER 2
CAPTURE REGISTER 1
CAPTURE REGISTER 0
MATCH REGISTER 3
MATCH REGISTER 2
MATCH REGISTER 1
MATCH REGISTER 0
CAPTURE CONTROL REGISTER
CONTROL
TIMER COUNTER
CSN
TCI
CE
=
=
=
=
INTERRUPT REGISTER
EXTERNAL MATCH REGISTER
MATCH CONTROL REGISTER
MAT[3:0]
INTERRUPT
CAP[3:0]
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]