NXP Semiconductors LPC24XX UM10237 - Manual (Page 425)

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UM10
237_
4
©
NXP
B.V
. 2009.
Al
l r
ig
h
ts
r
e
s
e
rv
ed.
User m
a
nu
al
Rev
. 04 — 26
Aug
u
st
2009
425 of
792
N
X
P Semi
conductor
s
UM10237
C
h
ap
te
r 1
6
: L
P
C2
4
XX UA
RT
0/
2/
3
Table 377. UART Register Map
Generic
Name Description Bit functions and addresses Acces
s Reset
value
[
1]
UARTn Register
Name & Address
MSB LSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
RBR
(DLAB=
0) Receiver Buffer
Register 8 bit Read Data RO NA U0RBR -
0xE000 C000
U2RBR - 0xE007 8000
U3RBR -
0xE007 C000
THR
(DLAB=
0) Transmit
Holding
Register 8 bit Write Data WO NA U0THR - 0xE000 C000
U2THR - 0xE007 8000
U3THR - 0xE007 C000
DLL
(DLAB=
1) Divisor Latch
LSB 8 bit Data R/W 0x01 U0DLL - 0xE000 C000
U2DLL - 0xE007 8000
U3DLL - 0xE007 C000
DLM
(DLAB=
1) Divisor Latch
MSB 8 bit Data R/W 0x00 U0DLM -
0xE000 C004
U2DLM - 0xE007 8004
U3DLM -
0xE007 C004
IER
(DLAB=
0) Interrupt Enable
Register Reserved Enable
Auto- Baud
Time- Out
Interrupt
Enable End
of Auto-
Baud
Interrupt
R/W 0x00 U0IER - 0xE000 C004
U2IER - 0xE007 8004
U3IER - 0xE007 C004
0 Enable
RX Line
Status
Interrupt
Enable
THRE
Interrupt
Enable RX
Data
Available
Interrupt
IIR Interrupt ID
Register Reserved ABTOInt ABEOint RO 0x01 U0IIR - 0xE000 C008
U2IIR - 0xE007 8008
U3IIR - 0xE007 C008
FIFOs Enabled 0 IIR3 IIR2 IIR1 IIR0
FCR FIFO Control
Register RX Trigger Reserved TX FIFO
Reset
RX FIFO
Reset
FIFO
Enable
WO 0x00 U0FCR - 0xE000 C008
U2FCR - 0xE007 8008
U3FCR - 0xE007 C008
LCR Line Control
Register DLAB Set
Break
Stick
Parity
Even
Parity
Select
Parity
Enable
Number
of Stop
Bits
Word Length Select R/W 0x00 U0LCR -
0xE000 C00C
U2LCR - 0xE007 800C
U3LCR -
0xE007 C00C