NXP Semiconductors LPC24XX UM10237 - Manual (Page 240)

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User manual Rev. 04 — 26 August 2009 240 of 792
NXP Semiconductors
UM10237
Chapter 11: LPC24XX Ethernet
7.4.3 Interrupt Clear Register (IntClear - 0xFFE0 0FE8)
The Interrupt Clear register (IntClear) is a Write Only register with an address of
0xFFE0 0FE8. The interrupt clear register bit definition is shown in
Table 11–230 .
The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears
the corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
7.4.4 Interrupt Set Register (IntSet - 0xFFE0 0FEC)
The Interrupt Set register (IntSet) is a Write Only register with an address of
0xFFE0 0FEC. The interrupt set register bit definition is shown in
Table 11–231 .
4 TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor
underrun situations. 0
5 TxErrorIntEn Enable for interrupt trigger on transmit errors. 0
6 TxFinishedIntEn Enable for interrupt triggered when all transmit descriptors
have been processed i.e. on the transition to the situation
where ProduceIndex == ConsumeIndex. 0
7 TxDoneIntEn Enable for interrupt triggered when a descriptor has been
transmitted while the Interrupt bit in the Control field of the
descriptor was set. 0
11:8 - Unused 0x0
12 SoftIntEn Enable for interrupt triggered by the SoftInt bit in the IntStatus
register, caused by software writing a 1 to the SoftIntSet bit in
the IntSet register. 0
13 WakeupIntEn Enable for interrupt triggered by a Wakeup event detected by
the receive filter. 0
31:14 - Unused 0x0
Table 229. Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description
Bit Symbol Function Reset
value
Table 230. Interrupt Clear register (IntClear - address 0xFFE0 0FE8) bit description
Bit Symbol Function Reset
value
0 RxOverrunIntClr Writing a ’1’ to one of these bits clears (0 to 7) the
corresponding status bit in interrupt status register
IntStatus. 0
1 RxErrorIntClr 0
2 RxFinishedIntClr 0
3 RxDoneIntClr 0
4 TxUnderrunIntClr 0
5 TxErrorIntClr 0
6 TxFinishedIntClr 0
7 TxDoneIntClr 0
11:8 - Unused 0x0
12 SoftIntClr Writing a ’1’ to one of these bits (12 and/or 13) clears the
corresponding status bit in interrupt status register
IntStatus. 0
13 WakeupIntClr 0
31:14 - Unused 0x0