NXP Semiconductors LPC24XX UM10237 - Manual (Page 324)

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User manual Rev. 04 — 26 August 2009 324 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
(1) Signal polarities may vary for some displays.
Fig 42. Vertical timing for STN displays
LCD_TIMV (VSW)
LCDDCLK
(panel clock)
LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP)
LCDFP
(vertical synch
pulse)
back porch
(defined in line clocks)
front porch
(defined in line clocks)
pixel data
and horizontal
controls for one
frame
one frame
all horizontal lines for one frame
see horizontal timing for STN displays
panel data clock active
(1) The active data lines will vary with the type of TFT panel.
(2) The LCD panel clock is selected and scaled by the LCD controler and used to produce LCDCLK.
(3) The duration of the LCDLP is controlled by the HSW field in the LCD_TIMH register.
(4) The polarity of the LCDLP signal is determined by the IHS bit in the LCD_POL regster.
Fig 43. Horizontol timing for TFT displays
pixel clock
(internal)
LCD_TIMH (HSW)
LCDLP
(lhorizontal
synch pulse)
LCD_TIMH (HBP)
LCD_TIMH(PPL) LCD_TIMH (HFP)
LCDDCLK
(panel clock)
horizontal back porch
(defined in pixel clocks)
horizontal front porch
(defined in pixel clocks)
one horizontal line of LCD data
LCDVD[23:0]
(panel data)
one horizontal line