NXP Semiconductors LPC24XX UM10237 - Manual (Page 736)

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User manual Rev. 04 — 26 August 2009 736 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
9.1 Hardware interrupt sequence flow
When a DMA interrupt request occurs, the Interrupt Service Routine needs to:
1. Read the DMACIntStatus Register to determine which channel generated the
interrupt. If more than one request is active it is recommended that the highest priority
channels be checked first.
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
generated due to the end of the transfer (terminal count). A HIGH bit indicates that the
transfer completed.
3. Read the DMACIntErrorStatus Register to determine whether the interrupt was
generated due to an error occurring. A HIGH bit indicates that an error occurred.
4. Service the interrupt request.
5. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
9.2 Interrupt polling sequence flow
Used when the GPDMA interrupt request signal is either masked out, disabled in the
interrupt controller or disabled in the processor. When polling the GPDMA, you must:
1. Read the DMACIntStatus Register. If none of the bits are HIGH repeat this step,
otherwise go to step 2. If more than one request is active it is recommended that the
highest priority channels be checked first.
2. Read the DMACIntTCStatus Register to determine whether the interrupt was
generated due to the end of the transfer (terminal count). A HIGH bit indicates that the
transfer completed.
3. Service the interrupt request.
4. For a terminal count interrupt write a 1 to the relevant bit of the DMACIntTCClr
Register. For an error interrupt write a 1 to the relevant bit of the DMACIntErrClr
Register to clear the interrupt request.
10. GPDMA data flow
This section describes the GPDMA data flow sequences for the four allowed transfer
types:
• Memory-to-peripheral.
• Peripheral-to-memory.
• Memory-to-memory.
• Peripheral-to-peripheral.
Each transfer type can have either the peripheral or the GPDMA as the flow controller so
there are eight possible control scenarios.
Table 32–676 indicates the request signals used for each type of transfer.